参数资料
| 型号： | SC4525CSETRT |
| 厂商： | Semtech |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 26.88 V |
| 输入电压： | 3 V ~ 28 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 1.3MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | SC4525CSEDKR |
SC4525C
Applications Information (Cont.)
Loop Compensation
The goal of compensation is to shape the frequency
It has an ESR zero F Z at
response of the converter so as to achieve high DC
accuracy and fast transient response while maintaining
loop stability (see Figure 7).
ω Z =
R ESR C O
CONTROLLER AND SCHOTTKY DIODE
It has a dominant low-frequency pole F P at
REF
+
CA
Rs
Io
ω p ≈
R C O
FB
-
EA
Vc
Vramp
PWM
MODULATOR
SW
L1
Vo
and double poles at half the switching frequency.
C5
R7
COMP
C8
Co
Resr
R4
R6
Including the voltage divider (R 4 and R 6 ), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
Figure 7. Block diagram of control loops
The block diagram in Figure 7 shows the control loops of a
buck converter with the SC4525C. The inner loop (current
loop) consists of a current sensing resistor (R s =3.53m W )
and a current amplifier (CA) with gain (G CA = 8.5). The
outer loop (voltage loop) consists of an error amplifier
(EA), a PWM modulator, and a LC filter.
Since the current loop is internally closed, the remaining
task for the loop compensation is to design the voltage
compensator (C 5 , R 7 , and C 8 ).
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F Z , and a high frequency pole
at F P . The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
60
NV
T ER
GA
MP
EN
SA
OP
AIN
For a converter with switching frequency F SW , output
inductance L , output capacitance C O and loading R, the
control (V C ) to output (V O ) transfer function in Figure 7 is
given by:
30
0
-30
Fp
CO
Fz1
ER
Fc
IN
Fp1
LO
CO
G
TO
RG
AIN
V o
V c
=
G PWM ( + s R ESR C O )
( + s / ω p ) ( + s / ω n Q + s 2 / ω n 2 )
-60
1K
10K
100K
Fz
Fsw/2
1M
10M
This transfer function has a finite DC gain
FREQUENCY (Hz)
Figure 8 — Bode plots for voltage loop design
G PWM ≈
R
G CA x R S
4
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