参数资料
| 型号： | SC4624AMLTRT |
| 厂商： | Semtech |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 4A 20MLPQ |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 5.5 V |
| 输入电压： | 2.3 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 2MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-MLPQ（4x4） |
| 其它名称： | SC4624AMLDKR |
SC4624A
POWER MANAGEMENT
Operation
Application Information (Cont.)
Transient response
SynchronizationFrequency
Synchronization operation mode is invoked by using an
external clock signal and is activated when the SYNC/EN
is pulled and held above 2V and held below 0.8V. The
range of synchronization frequency is from 200kHz to
2MHz.
A jitter happens when sync pulse clock edge is less than
120ns before the phase switches. It is caused by the
ground bounce of synchronization pulse coupled to PWM
comparator. Users try to avoid this application. (refer to
Figure 9).
Power Good Indicator
The PGOOD pin is an open-drain and incorporated window
comparators output. It’s is necessary that a pull-up
resistor from the PGOOD pin to the input supply for setting
the logic high level of the PGOOD signal. When FB voltage
is within + 10% setting output voltages typical, the output
of power good comparator becomes high impedance after
delay time. The PGOOD signal delay time is around 1024/
F OSC . In shutdown mode the power good output is actively
pulled low.
For example, 1MHz switching frequency applications, the
PGOOD delay time is around 1ms.
Thermal Shutdown
When the junction temperature rises up around 160°C,
the internal soft start voltage is held low, the internal high
side and low side MOSFETs are turned off and the output
voltage will fall to zero. Once the junction temperature
goes below hysteresis temperature around 10°C, the
regulator will restart. (refer to Figure 8).
Linear Mode Operation (100% duty)
The SC4624A can allows 100% duty cycle operation. The
Vout is,
where
R L : Output inductor DC resistance.
R DSH : Internal high side P-MOSFET resistance.
(refer to Figure11).
As Vin drops gradually and close to Vout, the buck regulator
will go into 100% duty cycle ratio. A matter needing
attention is internal high side PMOS has minimum off time
limitation and is related to duty cycle rate. T his condition
makes the working duty cycle perform at randon with the
output ripple increasing and a poor transient response.
Above phenomenon can be improved by larger output
capacitor and smaller output inductor. Users need to
verify whether above application condition has opposite
influence on entire circuit.
Over Current Protection
A over current setting is programmed by an external
resistor (R ISET ). It goes through internal sense resistor and
generates a voltage.
where
I : The current is generated by R ISET , and it is amplified
by internal current amplifier.
R ONSENSE : Internal sense resistor.
Output inductor current goes through internal high side
P-MOSFET and generate a voltage.
where
I L : Output inductor current.
R DSH(ON) : High side P-MOSFET conduction resistance.
After the high side PMOS turn on around 30ns, the OCP
comparator will compare between V2 and V1. When the
converter detects an over current condition (V2 > V1)
as shown in Figure 16, the SC4624A proceeds into the
cycle by cycle protection mode (Point B to Point C), which
responds to minor over current cases and the output
voltage is monitored.
If the over current and low output voltage (set at 60% of
nominal output voltage) occur at the same time, the SS
pin is pull low by an internal switch and the comp pin is
andthedevicesstops 3.3Vin,1.2Vo,Io=0to
0V, FB and SS voltage rise forward
pulled low Test condition: switching. Assume start 3A
from FB = R=F=2.5A/us,T1=T2=0.3ms 0.5V. Once
SS voltage exceeds 0.4V, the hiccup comparator becomes
enabled. The hiccup period is around 2 17 /F OSC . (Point C to
Point D).
For example, with a switching frequency application of
? 2008 Semtech Corp.
12
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