参数资料
| 型号： | SC4624AMLTRT |
| 厂商： | Semtech |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 4A 20MLPQ |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 5.5 V |
| 输入电压： | 2.3 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 2MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-MLPQ（4x4） |
| 其它名称： | SC4624AMLDKR |
SC4624A
POWER MANAGEMENT
Operation
Application Information (Cont.)
where
The design guidelines for the SC4624A applications are
as follows:
ω I =
ω Z 1 =
ω Z 2 =
ω P 1 =
ω P 2 =
1
R 7 ? ( C 1 + C 2 )
1
R 1 ? C 2
1
( R 7 + R 8 ) ? C 8
C 1 + C 2
R 1 ? C 1 ? C 2
1
R 8 ? C 9 8
1. Set the loop gain crossover corner frequency w C for
given switching corner frequency w S = 2 p fs,
2. Place an integrator at the origin to increase DC and
low frequency gains.
3. Select w Z1 and w Z2 such that they are placed near w O
to damp the peaking and the loop gain has a -20dB/
dec rate to go across the 0dB line for obtaining a wide
bandwidth.
4. Cancel the zero from C4’s ESR by a compensator pole
w P1 ( w P1 = w ESR = 1/(R C C 4 )).
5. Place a high frequency compensator pole w P2 ( w P2 =
p fs) to get the maximum attenuation of the switch-
ing ripple and high frequency noise with the adequate
phase lag at w C .
following loop gain:
1 +
? w I ? V I 1 +
1 +
V M w Z 1 w Z 2 R C ? C 4
T ( s ) = G PWM ? G COMP ( s ) ? G VD ( s ) = ? ? ?
1 + s 1 + s 2 L 1 C
1 +
? 1 +
s
1
1
s
s
R C ? C 4
V M
? w I ? V I 1 + 1 +
OMP ( s ) ? G VD ( = ) =
w Z 1 w Z 2
s
s
L
s
1 + ? 1 + 1 + s 1 + s 2 L 1 C
Afterthecompensation,theconverterwillhavethe
s s s L
w P 1 w P 2 R
1 +
s ? ? ?
w P 1 w P 2 R
s
1 s s 1
The compensated loop gain will be as given as show in
Figure 18.
where
G PWM = PWM gain.
V M = 1.0V, ramp peak to valley voltage of SC4624A.
Figure 18. Asymptotic Diagrams
of Power Stage and Loop Gain
? 2008 Semtech Corp.
15
www.semtech.com
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