参数资料
型号: SC667ULTRT
厂商: Semtech
文件页数: 43/47页
文件大小: 0K
描述: IC LED DRVR LMU 7CH MLPQUT20
特色产品: Semtech sc667 and sc668
标准包装: 1
拓扑: 线性(LDO),PWM
输出数: 11
内部驱动器:
类型 - 主要: 背光,LED 闪烁器,照明管理装置(LMU)
频率: 400kHz
电源电压: 2.9 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 20-UFQFN 裸露焊盘
供应商设备封装: 20-MLPQ(3x3)
包装: 标准包装
工作温度: -40°C ~ 85°C
其它名称: SC667ULDKR
SC667
Register Map (continued)
To calculate the voltage at the ADC input, the weights of
only the bits set to one are summed together and multi-
plied by the voltage provided by LDO4. The result is equal
to the analog voltage applied to the ADI pin. For example,
sink is floating, the ADP_EN bit is cleared automatically.
Any write operations to change the following bit combi-
nations in register 01h will also cause bank #1 to resume
the original setting:
if the value of register 13h reads AD OUT = 01111111,
and V LDO4 = 2.8V, the ADC input is at:
2.8 x (4 -1 + 8 -1 + 16 -1 + 32 -1 + 64 -1 + 128 -1 + 256 -1 ) = 1.38V.
?
?
?
DIS = 1, EN = 0, BANK1EN = 1
DIS = 0, EN = 1, BANK1EN = 1
DIS = 1, EN = 1, BANK1EN = 1
ADC Rising Threshold (14h)
This register contains the value AD RISE . When AD OUT rises
above AD RISE and AD_AUTO = 1, backlight bank #1 changes
to the target value in the bank #1 target register (06h).
AD_R7 through AD_R0 [D7:D0]
These are the 8 bits of AD RISE . AD_R7 is the MSB, and AD_R0
is the LSB.
ADC Falling Threshold (15h)
This register contains the value AD FALL . When AD OUT falls
below AD FALL and AD_AUTO = 1, backlight bank #1 changes
to the starting value in the bank #1 register (02h).
AD_F7 through AD_F0 [D7:D0]
These are the 8 bits of AD FALL . AD_F7 is the MSB, and AD_F0
is the LSB.
ADP and OLE Functions (16h)
ADP (Automatic Drop-out Protection) and OLE (Other
Lighting Effects) are controlled with this register. ADP
applies to bank #1 only.
ADP ensures current matching in the LEDs by responding
to a low battery voltage. ADP limits the maximum back-
light current to a level which ensures that backlight LEDs
maintain matched currents. The ADP feature also prevents
the ripple on a low battery from inducing flicker in the
LEDs. As the battery voltage gradually proceeds lower,
ADP gradually dims the backlights. The normal backlight
brightness is restored after the battery is recharged by
ADP_ACT Bit D6
This bit is a flag. A logic one indicates that ADP has been
activated. Once activated, the ADP is limiting the backlight
current. This flag bit is reset when ADP_EN = 0, or when
any bank#1 current sink is floating, or by writing any of the
following bit combinations in register 01h:
? DIS = 1, EN = 0, BANK1EN = 1
? DIS = 0, EN = 1, BANK1EN = 1
? DIS = 1, EN = 1, BANK1EN = 1
ADP_RATE Bit D5
This bit sets the time that elapses before backlight current
reduces after ADP activates. A logic one delays reduction
of current for 4ms. A logic zero delays reduction of current
for 256μs.
When a reduction in bank #1 backlight current becomes
necessary, the first step change is delayed for 4ms (logic
one) or 256μs (logic zero). If bank #1 continues to need a
current reduction after the delay time has elapsed, the
brightness setting is lowered by one step. If further reduc-
tions in current are needed, the second and all subsequent
reductions occur at a faster rate equal to1/4 of the initial
delay time. Further reductions in current will stop when
the backlight accuracy and matching have normalized.
When 4ms is selected, the 1 st delay = 4ms, and the 2 nd and all
subsequent delays = 1ms. When 256μs is selected, the 1 st
delay = 256μs, and the 2 nd and all subsequent delays = 64μs.
writing a logic zero to the ADP_EN bit.
Bank #1 will try to resume the original backlight current
setting whenever ADP_EN = 0. Also, if any bank #1 current
43
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