参数资料
型号: SC811ULTRT
厂商: Semtech
文件页数: 15/23页
文件大小: 0K
描述: IC BATTERY MANAGEMENT
标准包装: 1
系列: *
其它名称: SC811ULDKR
SC811 / SC813
Applications Information (continued)
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R IPRGM (k Ω ), R-tol = 1%
Figure 3a — Termination Current Tolerance vs.
Programming Resistance, Low Resistance Range
the nominal termination current versus nominal R IPRGM
resistance as the center plot and two theoretical limit plots
indicating maximum and minimum current vs. nominal
programming resistance. These plots are derived from
models of the expected worst-case contribution of error
sources depending on programmed current. The current
range includes the uncertainty due to a 1% tolerance
resistor. The dots on each plot indicate the currents
obtained with standard value 1% tolerance resistors.
Figures 3a and 3b show low and high resistance ranges,
respectively.
Tri-level Logical Input Pins
The MODE and ENB pins are tri-level logical inputs. They
are designed to interface to a processor GPIO port that is
powered from a peripheral supply voltage as low as 1.8V
or as high as a fully charged battery. While a connected
GPIO port is configured as an output, the processor writes
0 to select ENB or MODE low-range, and 1 to select high-
range. The GPIO port is configured as an input to select
mid-range.
These pins can also be permanently grounded to select
low-range or left unconnected to select mid-range for
fixed mode operation. The MODE pin can also be perma-
nently connected to a logical high voltage source, such as
BAT or a regulated peripheral supply voltage.
The equivalent circuit looking into these pins is a variable
resistance, minimum 15kΩ, to an approximately 1V source.
R IPRGM (k Ω ), R-tol = 1%
Figure 3b — Termination Current Tolerance vs.
Programming Resistance, High Resistance Range
The input will float to mid range whenever the external
driver sinks or sources less than 5μA, a common worst-
case characteristic of a high impedance GPIO, or a weak
pull-up or pull-down GPIO, configured as an input. The
driving GPIO must be able to sink or source at least 75μA
to ensure a low or high state, respectively, although the
drive current is typically far less. (See the Electrical
Characteristics table.)
Mode Input
The MODE pin is a tri-level logical input. When driven high
(V MODE > Min V IH ), the SC811/3 will operate in USB High
Power mode. If the MODE input voltage is within its speci-
fied mid range (Min V IM < V ENB < Max V IM ), either by floating
(by reconfiguring its GPIO as an input) or by being exter-
nally forced, the SC811/3 will operate in USB Low Power
mode. When driven low (V MODE < Max V IL ), the SC811/3 will
operate in adapter mode.
When there is no charging source present, when the
charger is disabled, or when operating in the monitor
state (described in a later section), the MODE pin enters a
high impedance state, suspending the tri-level functional-
ity. Upon re-charge or re-enabling the charger, the MODE
pin tri-level interface is reactivated.
Typically a processor GPIO port direction defaults to input
upon processor reset, or is high impedance when un-
powered. This is the ideal initial condition for driving the
MODE pin, since this will select USB Low Power mode,
? 2008 Semtech Corporation
15
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