参数资料
型号: SCAN18374TSSCX
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 总线收发器
中文描述: SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO56
封装: 0.300 INCH, MO-118, SSOP-56
文件页数: 1/12页
文件大小: 99K
代理商: SCAN18374TSSCX
2000 Fairchild Semiconductor Corporation
DS010963
www.fairchildsemi.com
October 1991
Revised May 2000
SCAN18374
T
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e
Fl
ip-
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Out
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SCAN18374T
D-Type Flip-Flop with 3-STATE Outputs
General Description
The SCAN18374T is a high speed, low-power D-type flip-
flop featuring separate D-type inputs organized into dual 9-
bit bytes with byte-oriented clock and output enable control
signals. This device is compliant with IEEE 1149.1 Stan-
dard Test Access Port and BOUNDARY-SCAN Architec-
ture with the incorporation of the defined BOUNDARY-
SCAN test logic and test access port consisting of Test
Data Input (TDI), Test Data Out (TDO), Test Mode Select
(TMS), and Test Clock (TCK).
Features
s IEEE 1149.1 (JTAG) Compliant
s Buffered positive edge-triggered clock
s 3-STATE outputs for bus-oriented applications
s 9-bit data busses for parity applications
s Reduced-swing outputs source 32 mA/sink 64 mA
s Guaranteed to drive 50
transmission line to TTL input
levels of 0.8V and 2.0V
s TTL compatible inputs
s 25 mil pitch SSOP (Shrink Small Outline Package)
s Includes CLAMP and HIGHZ instructions
s Member of Fairchild’s SCAN Products
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Truth Tables
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= L-to-H Transition
Order Number
Package Number
Package Description
SCAN18374TSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names
Description
AI(0–8), BI(0–8)
Data Inputs
ACP, BCP
Clock Pulse Inputs
AOE1, BOE1
3-STATE Output Enable Inputs
AO(0–8), BO(0–8)
3-STATE Outputs
Inputs
AO(0–8)
ACP
AOE1
AI(0–8)
XHX
Z
LL
L
LH
H
Inputs
BO(0–8)
BCP
BOE1
BI(0–8)
XHX
Z
LL
L
LH
H
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