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参数资料
| 型号： | SCANPSC100FSCX |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封装： | 0.300 INCH, MS-013, SOIC-28 |
| 文件页数： | 18/21页 |
| 文件大小： | 208K |
| 代理商： | SCANPSC100FSCX |
www.fairchildsemi.com
6
SCAN
PSC100
F
Parallel Processor Interface (PPI) (Continued)
TIMING WAVEFORMS
FIGURE 2. Write Cycle
FIGURE 3. Read Cycle
Note 1: Valid data is provided on the RDY line a tPD1 after R/W is asserted LOW or a tPD2 after valid data is decoded on A2:0. The RDY line will remain HIGH
until the addressed register is ready to participate in the write operation. This condition only applies when writing to a shifter/buffer and is eliminated (i.e.,
RDY will go LOW immediately once valid) when using shifter/buffer status polling (discussed later in this datasheet).
Note 2: Valid data will not appear on D7:0 (and RDY will remain HIGH) until the addressed register is ready to participate in the read operation. When the
addressed register becomes ready (i.e., a byte is available to be read), valid data will be placed on the D7:0 bus and the RDY pin will go LOW allowing the
bus cycle to continue. This read cycle delay only applies when reading the TDI shifter/buffer and is eliminated when using shifter/buffer status poling.
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