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参数资料
| 型号： | SCE5785 |
| 厂商： | SIEMENS A G |
| 元件分类： | 显示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, SOFT ORANGE, 4.57 mm |
| 封装： | PLASTIC, DIP-26 |
| 文件页数： | 9/13页 |
| 文件大小： | 295K |
| 代理商： | SCE5785 |
2–191
SCE5780/1/2/3/4/5
Top View
Pin Assignment
Figure 5. Dot Matrix Format
Pin
Function
Pin
Function
1
CLKSEL
14
Serial Data
2
VCC (Logic)
15
No connect
3VLL (LED)
16
Serial CLK
4
No pin
17
No pin
5
No pin
18
No pin
6
No pin
19
No pin
7
No pin
20
No pin
8
No pin
21
No pin
9
No pin
22
No pin
10
No pin
23
No pin
11
Load
24
Reset
12
GND
25
CLK I/O
13
GND
26
No connect
0
1
2
3
4
5
6
7
0.100
(2.54)
0.028
(.72)
typ.
0.022
(.57) typ.
0.180
(4.57)
R1
C1 C2 C3 C4 C5
R0
R2
R3
R4
R5
R6
Pin Denitions
Pin
Function
Denitions
1
CLKSEL
H=internal clock, L=external clock
2VCC (Logic)
Logic power supply
3VLL (LED)
LED power supply
4–10
No pin
No pins in these postions
11
Load
Low input enables data clocking
into the 8-bit serial shift register.
When Load goes high, the con-
tents of the 8-bit serial shift regis-
ter will be decoded.
12,13
GND
Power supply ground
14
Serial Data
Serial data input
15, 16
No connect
Pins have no function
16
Serial CLK
For loading data into the 8-bit
serial register on a low to high
transition.
17–23
No pin
No pins in these positions
24
Reset
Asynchronous input, when low
will clear the Multiplex Counter,
User RAM, and Data Register.
Control Word Register is set to
100% brightness, maximum peak
current, and oscillator divided by
1. The display blanked.
25
CLK I/O
Outputs master clock or input
external clock for display multi-
plexing.
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