参数资料
型号: SCF5249LAG120
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 120 MHz, RISC PROCESSOR, PQFP144
封装: LEAD FREE, QFP-144
文件页数: 2/56页
文件大小: 918K
代理商: SCF5249LAG120
SCF5249 Integrated ColdFire Microprocessor Data Sheet, Rev. 3
SCF5249 Functional Overview
Freescale Semiconductor
10
The CD-ROM decoder performs following functions in hardware:
Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
The CD-ROM encoder performs following functions in hardware:
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of
performance for single-speed.
5.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
5.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
37 Mbits/second are possible at a CPU clock of 140 MHz. The QSPI supports master mode operation only.
5.15 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer
for use in any of three modes:
1. Timer Capture. This mode captures the timer value with an external event.
2. Output Capture. This mode triggers an external signal or interrupts the CPU when the timer
reaches a set value
3. Event Counter. This mode counts external events.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock
(CPU clock / 2), the programmable timer-output pins either generate an active-low pulse or toggle the
outputs.
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SCF5250CAG120 32-BIT, 120 MHz, MICROPROCESSOR, PQFP144
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