参数资料
型号: SCG4525
厂商: CONNOR WINFIELD CORP
元件分类: 时钟及定时
英文描述: 4000/14000/40000 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), DSO18
封装: 1 X 1.025 INCH, 0.45 INCH HEIGHT, SMT-18
文件页数: 10/16页
文件大小: 2334K
代理商: SCG4525
Preliminary Data Sheet #: SG069
Page 3 of 16
Rev: P00
Date: 02/06/03
Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
NOTES:
1.0
Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0
Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0
3db loop response.
4.0
50-ohm load biased to 1.3 volts.
5.0
Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
6.0
If the selected reference is removed system response to the ALARM must be less than 100ns.
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
V
cc
Power Supply Voltage
-0.5
-
+4.0
Volts
1.0
V
i
Input Voltage
-0.5
-
+5.5
Volts
1.0
T
s
Storage Temperature
-65.0
-
+100
°C
1.0
Operating Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
V
cc
Power Supply Voltage
3.135
3.3
3.465
Volts
2.0
I
cc
Power Supply Current
-
230
-
mA
4.0
T
o
Temperature Range
0
-
70
°C
f
in
Input Frequency
-
19.44
-
MHz
f
out
LVPECL Synchronized Output Frequency
-
77.76 or 155.52
-
MHz
f
ref
CMOS Output Frequency
-
77.76
-
MHz
f
fr
Free Run Frequency
-20
-
20
ppm
f
cap
Capture/pull-in range
-25
-
25
ppm
f
bw
Jitter Filter Bandwidth
-
10
Hz
3.0
t
jtol
Input Jitter Tolerance
1
-
s
(Input Jitter Frequencies
≥ 10 Hz)
t
rf
Output Rise and Fall Time (20% 80%)
100
225
350
ps
4.0
DC
Output Duty Cycle
40
50
60
%
MTIE
sr
MTIE at Synchronization Rearrangement
GR-253-CORE.1999 R5-136
5.0, 6.0
t
aq
Acquisition Time
Apprx. 1 sec. frequency lock when reference is stepped up or down 10ppm
< 1 sec. phase lock when switching between same frequency references
30 - 60 sec. phase lock during start-up or when locking from Free Run
Output Jitter Specifications
Table 3
Jitter BW 10 Hz - 1 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
pS (RMS)
m UI
pS (RMS)
m UI
LVPECL (Synchronized Output)
77.76
10 Typ.
0.776 Typ.
1 Max.
0.076 Max.
155.52
10 Typ.
1.556 Typ.
1 Max.
0.156 Max.
CMOS (Filtered Reference Output)
77.76
25 Typ.
1.944 Typ.
3 Typ.
0.233 Typ.
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