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参数资料
| 型号： | SCG4525 |
| 厂商： | CONNOR WINFIELD CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | 4000/14000/40000 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), DSO18 |
| 封装： | 1 X 1.025 INCH, 0.45 INCH HEIGHT, SMT-18 |
| 文件页数： | 9/16页 |
| 文件大小： | 2334K |
| 代理商： | SCG4525 |
Preliminary Data Sheet #: SG069
Page 2 of 16
Rev: P00
Date: 02/06/03
Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
General Description
The SCG4525 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled. The SCG4525 also provides
a CMOS Output @ 77.76 MHz on the REF_OUT pin.
The SCG4525 can lock to one of two external
references, which is selectable using the SEL
AB input
select pin. The unit has a fast acquisition time of about
1 second and it is tolerant of different reference duty
cycles.
The SCG4525 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FR
status
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to ±20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1.00” x 1.025” x 0.45”
on a 6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Maximum Dimension Package Outline
Figure 1
Block Diagram
Figure 2
8 KHz PHASE
ALIGNER
REFB
REFA
SEL AB
ANALOG
FILTER
Q
QN
1 / N
ALARM
LOW JITTER
VCXO
FREE RUN STATUS
77.76 MHz CMOS
on REF_OUT
PIN
FORCE
FREE RUN
ENABLE/
TRI-STATE
DPFD
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