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参数资料
| 型号： | SD-14531D2-202 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PDIP36 |
| 封装： | KOVER, DDIP-36 |
| 文件页数： | 3/16页 |
| 文件大小： | 272K |
| 代理商： | SD-14531D2-202 |
ProASIC3/E Flash Family FPGAs
v2.1
1-5
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost Empty (AEMPTY) and Almost Full (AFULL) flags in
addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters
necessary for generation of the read and write address
pointers. The embedded SRAM/FIFO blocks can be
cascaded to create larger configurations.
PLL and CCC
ProASIC3 devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASIC3 family contains six CCCs. One CCC (center west
side) has a PLL. The A3P030 does not have a PLL.
The six CCC blocks are located at the four corners and the
centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and
the east CCC allow simple clock delay operations as well
as clock spine access.
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several inputs located near the
CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock delay adjustment via programmable and
fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew
minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL
only)
Low output jitter: worst case < 2.5% × clock period
peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time = 300 s (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter—
allowable input jitter is up to 1.5 ns (for PLL only)
Four
precise
phases;
maximum
misalignment
between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC) (for PLL only)Global Clocking
ProASIC3 devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock
distribution network.
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks. The VersaNets can be driven by the CCC or
directly accessed from the core via multiplexers (MUXes).
The VersaNets can be used to distribute low-skew clock
signals or for rapid distribution of high fanout nets.
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). ProASIC3 FPGAs support many different
I/O standards—single-ended and differential.
The I/Os are organized into banks, with two or four
banks per device. The configuration of these banks
determines the I/O standards supported.
Each I/O module contains several input, output, and
enable
registers.
These
registers
allow
the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, BLVDS,
and M-LVDS I/Os for point-to-point communications
ProASIC3 banks for the A3P250 device and above
support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-
LVDS can support up to 20 loads.
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