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参数资料
| 型号： | SD-15900JH-300 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC84 |
| 文件页数： | 5/8页 |
| 文件大小： | 373K |
| 代理商： | SD-15900JH-300 |
5
66
PIN
43
24
PIN
1
MODE
FUNCTION
CLKIN
COURSE
FUNCTION
HOLD
67
44
25
2
VCC
RES_L
VCC
NC
68
45
3
VCC
NC
VCC
NC
69
46
27
4
OUT<9>
VCC
FINEHI
VCC
70
47
28
5
OUT<8>
ENHIGH
FINELO
NC
71
48
29
6
OUT<7>
ENMID
NC
72
49
30
7
NC
ENLOW
NC
73
50
31
8
NC
OUT<22>
NC
74
51
32
9
NC
OUT<21>
NC
75
52
33
10
NC
OUT<20>
VPP
NC
76
53
34
11
OUT<6>
OUT<19>
NC
77
54
35
12
OUT<5>
OUT<18>
NC
78
55
36
13
OUT<4>
OUT<17>
NC
IN<1>
79
56
37
14
OUT<3>
OUT<16>
NC
IN<2>
80
57
38
15
OUT<2>
OUT<15>
NC
IN<3>
65
64
63
62
84
61
83
60
82
59
81
58
23
22
21
20
42
19
41
18
40
17
39
16
OUT<10>
NC
OUT<11>
OUT<12>
NC
GND
NC
GND
OUT<13>
OUT<1>
OUT<14>
INH
IN<8>
IN<7>
IN<6>
CLKOUT
GND
NC
GND
IN<5>
NC
IN<4>
26
TABLE 5. PINOUTS
(PLASTIC J-LEAD - FIGURE 5)
FUNCTION
PIN FUNCTION
OUT<22>
L11
OUT<18>
K11
OUT<10>
G11
OUT<8>
F11
MODE
E11
OUT<7>
D11
OUT<5>
C11
NC
A11
B11
OUT<21>
L10
OUT<17>
K10
OUT<2>
OUT<13>
A10
NC
J10
B3
OUT<20>
OUT<11>
L9
NC
H10
A3
OUT<16>
GND
K9
NC
G10
F10
L2
OUT<9>
VCC
G9
VPP
E10
K2
NC
OUT<6>
F9
NC
D10
J2
VCC
NC
E9
NC
C10
H2
OUT<4>
NC
B9
VCC
B10
G2
OUT<14>
OUT<1>
A9
J11
OUT<19>
L8
OUT<12>
OUT<15>
K8
H11
OUT<3>
B8
CLKOUT
ENHIGH
A8
L5
NC
L7
GND
VCC
K7
K5
NC
J7
NC
C7
J5
GND
B7
NC
ENMID
A7
C5
CLKIN
L6
NC
VCC
NC
K6
A5
B5
NC
J6
FINELO
NC
C6
L4
ENLOW
NC
A6
B6
FINEHI
NC
F2
K4
GND
E2
NC
D2
B4
NC
C2
NC
B2
A4
RES_L
A2
NC
COURSE
INH
L1
L3
K3
IN<8>
K1
NC
IN<7>
J1
G3
IN<6>
H1
NC
IN<5>
G1
F3
VCC
F1
GND
IN<4>
E1
E3
IN<3>
D1
NC
IN<2>
C1
C3
HOLD
IN<1>
B1
A1
TABLE 4. PINOUTS
(CERAMIC PGA - FIGURE 4)
PIN
IN<1:8>
OUT<1:22>
Output data word. (NOTE: Bit 1 is the
Most Significant Bit).
TABLE 3. SD-15900 SIGNAL FUNCTIONS
INH
Active low output indicating combiner
output word is NOT ready.
PIN
HOLD
DESCRIPTION
COURSE
Active low output used to enable exter-
nal device output drivers for course byte
data.
FINEHI
FINELO
Active low output used to enable exter-
nal device output drivers for fine low
byte data.
ENHIGH
Active low input used to enable the
most significant byte of the output word.
ENMID
Active low input used to enable the mid-
dle byte of the output word.
ENLOW
CLKOUT
Output used to select internal clock by
strapping to CLKIN.
CLKIN
Clock input. Can use internal clock by
strapping CLKOUT to CLKIN.
MODE
Used for internal diagnostics. This must
be tied to circuit ground for normal
operation.
VPP
Used for device programming. This pin
must be tied to circuit VCC (digital +5V
supply) for normal operation.
RES_L
Digital input for course and fine data.
(NOTE: Bit 1 is the Most
Significant Bit).
Active low input to the combiner indicat-
ing that external device is busy reading
combiner outputs and that internal data
should be held steady.
Active low output used to enable exter-
nal device output drivers for fine high
byte.
Active low input used to enable the
least significant byte of the output
word.
Reset Line (Low = Reset); Tie high for
nomal operation.
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