参数资料
型号: SDCFAB-016G
厂商: SANDISK CORP
元件分类: 存储控制器/管理单元
英文描述: IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, XMA50
封装: PC CARD-50
文件页数: 13/47页
文件大小: 397K
代理商: SDCFAB-016G
SanDisk CompactFlash Card OEM Product Manual
Interface Description
02/09, Rev. 1.0 ii 2007 - 2009 SanDisk Corporation. SanDisk Confidential, subject to all applicable non-disclosure agreements.
20
Signal Name
Dir.
Pin
Description
RESET
(PC Card Memory Mode)
I
41
The CompactFlash Storage Card or CF+
Card is Reset when the RESET pin is high
with the following important exception:
The host may leave the RESET pin open
or keep it continually high from the
application of power without causing a
continuous Reset of the card. Under
either of these conditions, the card shall
emerge from power-up having completed
an initial Reset.
The CompactFlash Storage Card or CF+
Card is also Reset when the Soft Reset bit
in the Card Configuration Option Register
is set.
RESET
(PC Card I/O Mode)
This signal is the same as the PC Card
Memory Mode signal.
-RESET
(True IDE Mode)
In the True IDE Mode, this input pin is the
active low hardware reset from the host.
VCC
(PC Card Memory Mode)
--
13,38
+5 V, +3.3 V power.
VCC
(PC Card I/O Mode)
This signal is the same for all modes.
VCC
(True IDE Mode)
This signal is the same for all modes.
-VS1
-VS2
(PC Card Memory Mode)
O
33
40
Voltage Sense Signals. -VS1 is grounded
on the Card and sensed by the Host so
that the CompactFlash Storage Card or
CF+ Card CIS can be read at 3.3 volts
and -VS2 is reserved by PCMCIA for a
secondary voltage and is not connected
on the Card.
-VS1
-VS2
(PC Card I/O Mode)
This signal is the same for all modes.
-VS1
-VS2
(True IDE Mode)
This signal is the same for all modes.
-WAIT
(PC Card Memory Mode –
Except Ultra DMA
Protocol Active)
O
42
The -WAIT signal is driven low by the
CompactFlash Storage Card or CF+ Card
to signal the host to delay completion of a
memory or I/O cycle that is in progress.
-WAIT
(PC Card I/O Mode –
Except Ultra DMA
Protocol Active)
This signal is the same as the PC Card
Memory Mode signal.
IORDY
(True IDE Mode – Except
Ultra DMA Protocol
Active)
In True IDE Mode, except in Ultra DMA
modes, this output signal may be used as
IORDY.
-DDMARDY
(All Modes – Ultra DMA
Write Protocol Active)
In all modes, when Ultra DMA mode DMA
Write is active, this signal is asserted by
the device during a data burst to indicate
that the device is ready to receive Ultra
DMA data out bursts. The device may
negate -DDMARDY to pause an Ultra
DMA transfer.
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