参数资料
型号: SED1231DBB
元件分类: 显示控制器
英文描述: 21 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC171
封装: GOLD BUMP, DIE-171
文件页数: 3/8页
文件大小: 255K
代理商: SED1231DBB
3
SED1230 Series
s PAD SPECIFICATION
SED1230D** 1/30 duty 12 columns + 1 signal column
SED1231D** 1/23 duty 12 columns + 1 signal column
SED1232D** 1/16 duty 12 columns + 1 signal column
SED1233D** 1/16 duty 16 columns
#1 Column for CGROM pattern change
Chip size:
10.23
× 3.11 mm
Pad pitch:
110
m (Min.)
Chip thickness:
625
± 25 m (SED123*D*A, SED123*D*B)
525
± 25 m (SED123*D*C, SED123*D*E)
1) A1 pad specification (SED123*
D*A)
Pad size: A 86
m × 135 m
B 135
m × 86 m
2) Au bump specification (SED123*
D*B*)
For reference:
Bump sizeA 80
m × 129 m
B 129
m × 80 m
Bump height 22.5
m ± 5.5 m
s ABSOLUTE MAXIMUM RATINGS
Notes: 1. All the voltage values are based on VDD = 0 V.
2. For voltages of V1, V2, V3 and V4, keep the condition of VDD
≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 at all times.
3. If the LSI is used exceeding the absolute maximum ratings, it may lead to permanent destruction.
In ordinary operation, it is desirable to use the LSI in the condition of electrical characteristics. If the LSI
is used out of this condition, it may cause a malfunction of the LSI and have a bad effect on the reliability
of the LSI.
Rating
Symbol
Value
Unit
Power supply voltage (1)
VSS
–6.0 to +0.3
V
Power supply voltage (2)
V5
–16.0 to +0.3
V
Power supply voltage (3)
V1, V2, V3, V4
V5 to +0.3
V
Input voltage
VIN
VSS–0.3 to +0.3
V
Output voltage
VO
VSS–0.3 to +0.3
V
Operating temperature
Topr
–30 to +85
°C
Storage temperature
TCP
Tstr
–55 to +100
°C
Bare chip
–75 to +125
(VCC) VDD
(GND) VSS
VDD
V5
(0,0)
173
174
193
1
58
69
85
86
相关PDF资料
PDF描述
SED1233DAE DOT MAT LCD DRVR AND DSPL CTLR, UUC171
SED1232T 21 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC
SED1233T DOT MAT LCD DRVR AND DSPL CTLR, UUC
SED1230T 28 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC
SED1231T 21 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC
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