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参数资料
| 型号： | SED1240TXX |
| 元件分类： | 显示控制器 |
| 英文描述： | 32 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC |
| 封装： | TCP |
| 文件页数： | 5/67页 |
| 文件大小： | 736K |
| 代理商： | SED1240TXX |
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EPSON
8–13
SED1240 Series
SED1240
Series
DESCRIPTION OF FUNCTIONS
MPU Interfaces
In the SED1240 series, an MPU type, interface bit length and interface method can be selected depending on pins IF, P/
S and C86.
Selection of MPU
In the SED1240 series, when parallel input is selected (P/S = “H”), pin C86 has an MPU selecting function.
When either “H” or “L” is selected as the polarity of pin C86, the 80 series MPU or 68 series MPU can be selected as shown
in Table 1.
Selection of an interface bit length (8 bits, 4 bits) is performed by pin IF.
Table 1
Selection of interface type
In the SED1240 series, it is possible to select an 8-bit or 4-bit parallel interface or a serial interface that permits a data
transfer through a serial input (SI). As the selecting method, set the polarity of pins of P/S and IF to “H” or “L”.
Table 2
Interface with 4-bit MPU
When data is transferred by a 4-bit interface (IF = 0), 8-bit commands, data and addresses are divided into 2 parts for
transfer. A timing example of the 80 series MPU is shown below.
Note: For continuous writing, perform it after securing a time exceeding the system cycle time (tcyc).
Serial interface (P/S = “L”)
The serial interface consists of an 8-bit shift register and a 3-bit counter, and becomes ready to accept an SI input or SCL
input in the chip selected state (CS = “L”).
Unless any chip is selected, the shift register and the counter are reset to the initial state. (Refresh state)
Data is input in the order of D7, D6, .... D0 from the serial data input pin (SI) at the rise of the serial clock (SCL). At the
rising edge of the 8th serial clock, the data is converted into parallel data.
Whether the serial data input (SI) is display data or a command is identified and judged by A0 input. When A0 = “H”,
the data becomes display data. When A0 = “L”, the data becomes a command. The A0 input is read and identified at the
rise of the 8
× nth serial clock (SCL) after chip selection.
MPU type
Pin C86 state
Polarity of RES function input
MPU connection
A0
WR
CS
D0 to D7
68 series
High level
Low level active
A0
E
CS
D0 to D7
80 series
Low level
A0
WR
CS
D0 to D7
Interface Interface
Selecting pin state
Pin state
type
bit length
P/S
IF
CS
A0
WR
D7
D6
D5
D4
D3
D2
D1
D0
Parallel
8 bits
H
CS
A0
WR
D7
D6
D5
D4
D3
D2
D1
D0
Parallel
4 bits
H
L
CS
A0
WR
D7
D6
D5
D4
OPEN or H or L
Serial
1 bit
L
H or L
CS
A0 H or L
SI
SCL
OPEN or H or L
CS
WR
D7 to D4
Upper (D7 to D4)
Lower (D3 to D0)
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| SED1241DAB | 24 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC210 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SED1278 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D | 制造商:EPSON 制造商全称:EPSON 功能描述:Dot Matrix LCD Controller Driver |
| SED1278D0A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D0B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D0C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
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