- 您现在的位置：买卖IC网 > PDF目录69341 > SED1241DAB 24 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC210 PDF资料下载
参数资料
| 型号： | SED1241DAB |
| 元件分类： | 显示控制器 |
| 英文描述： | 24 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC210 |
| 封装： | DIE-210 |
| 文件页数： | 50/67页 |
| 文件大小： | 736K |
| 代理商： | SED1241DAB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
8–54
EPSON
SED1240 Series
*1: The wide operating voltage range is guaranteed
except the case where a sudden voltage change
occurs during MPU access.
In the low-supply voltage data holding characteristic,
it is applied in the sleep mode and MPU access
cannot be guaranteed
*2: At triple boosting, take care about supply voltage
VSS2 so that it may not exceed the V5 operating
voltage range.
*3: D0 to D5, D6 (SCL), D7 (SI), A0, RES, CS, WR (E),
P/S, IF. C86. CK
*4: This is a resistance value when a voltage of 0.1 V is
applied between output pins SEGn, SEGSn, COMn,
and COMSn, and each power pin (V1, V2, V3, V4).
This is specified within the range of operating
voltage (2).
RON = 0.1 V /
I
(
I: A current flowing when 0.1 V is
applied between the power supply and
the output)
*5: Applies under the following conditions:
No access from MPU during all characters ‘H’
display
The built-in circuit and oscillating circuit are
operating.
CGRAM unused, HPM = 0 specified, VSS = -3.0
*6: Applies under the following conditions:
Standby mode
ALl the built-in power circuit off
Display off
Oscillating circuit on
*7: Indicates that fcyc is used for writing at all times.
The current consumption during access is
approximately proportional to the access frequency
(fcyc).
*8: Specifies the RES signal minimum pulse width. To
perform resetting, it is necessary to input the pulse
having a width of
tRW or more. Original, the method
for reset case 1 is used, but the method for reset case
2 can also be used if the reset start time condition of
tRES or less is satisfied.
*9: The boosting circuit performs boosting, using voltage
between the VDD and VSS2 as source voltage. Check
the VSS2 input voltage to ensure that it does not
exceed VOUT absolute maximum rating, or the
operating voltage range of the VSS system (VSS) and
V5 system (V5).
*10: Frequency
fOSC of the internal circuit drive
oscillating circuit and boosting clock fBST vary
according to the type. The following shows the
relationship between the oscillating circuit
fOSC and
boosting clock f BST:
fOSC = (number of digits)
× (1/duty) × fFR
fBST = (1/2)
× (1/number of digits) × fOSC
*11: Enter the following input when performing
operations by the external clock, without using the
built-in oscillating circuit:
Duty = (
th/tOSC)
× 100 = 20 to 30%
fOSC = 1/tOSC
VDD
RES
Power
supply
VSS
VDD
VSS
VDD
tRW
tRES
tRW
VSS
VDD
RES
Power
supply
Reset case 2
Reset case 1
tOSC
th
*12: Adjust the V5 voltage regulating circuit within the
voltage follower operating voltage range.
* All timing are specified on the basis of 20% and 80% of VSS.
相关PDF资料 |
PDF描述 |
|---|---|
| SED1241TXX | 24 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC |
| SED1278D0G | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC |
| SED1278F0H | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80 |
| SED1278D | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| SED1278F | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SED1278 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D | 制造商:EPSON 制造商全称:EPSON 功能描述:Dot Matrix LCD Controller Driver |
| SED1278D0A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D0B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
| SED1278D0C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS DOT MATRIX LCD CONTROLLER DRIVER |
发布紧急采购，3分钟左右您将得到回复。