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参数资料
| 型号： | SED1522DOB |
| 元件分类： | 显示控制器 |
| 英文描述： | DOT MAT LCD DRVR AND DSPL CTLR, UUC100 |
| 封装： | 4.80 X 7.04 MM, 0.525 MM HEIGHT, GOLD BUMP, DIE-100 |
| 文件页数： | 7/10页 |
| 文件大小： | 40K |
| 代理商： | SED1522DOB |
348
AC Characteristics
° Read/Write timing for the 80-port MPU
Parameter
Signal
Symbol
Condition
Min
Typ
Max
Unit
Address hold time
A0, CS
tAH8
10
—
ns
Address set-up time
tAW8
20
—
ns
System cycle time
WR, RD
tCYC8
1000
—
ns
Control pulse width
tCC
200
—
ns
Data set-up time
tDS8
80
—
ns
Data hold time
D0~D7
tDH8
10
—
ns
RD access time
tACC8
CL=100pF
——
90
ns
Output disable time
tOH8
10
—
60
ns
*2. The ratings when VSS = –3.0V are approximately 100% higher than when VSS = –5.0V.
*3. The rise or fall time of input signals should be less than 15ns.
(Ta = –20 to 75
°C, VSS = –5.0V±10%)
° Read/Write timing for the 68-port MPU
Parameter
Signal
Symbol
Condition
Min
Typ
Max
Unit
System cycle time
A0, CS
tCYC6 *4
1000
—
ns
Address set-up time
R/W
tAW6
20
—
ns
Address hold time
tAH6
10
—
ns
Data set-up time
tDS6
80
—
ns
Data hold time
D0~D7
tDH6
10
—
ns
Output disable time
tOH6
CL=100pF
10
—
60
ns
Access time
tACC6
——
90
ns
Enable pulse width
READ
EtEW
100
—
ns
WRITE
80
—
ns
*4 tCYC6 indicates the cycle during which CS/E are HIGH; it does not indicate the cycle of the E signal.
*5 The ratings when VSS = –3.0V are approximately 100% higher than when VSS = –5.0V.
*6 The rise or fall time of input signals should be less than 15ns.
(Ta = –20 to 75
°C, VSS = –5.0V±10%)
° Control timing for 80-port/68-port display
Parameter
Signal
Symbol
Condition
Min
Typ
Max
Unit
LOW pulse width
tWLCL
35
—
s
HIGH pulse width
CL
tWHCL
(Input timing)
35
—
s
Rising time
tr
—
30
150
ns
Falling time
tf
—
30
150
ns
(Input timing)
–2.0
0.2
2.0
s
FR delay time
FR
tDFR
(Output timing),
—
0.2
0.4
s
CL=100pF
(Ta = –20 to 75
°C, VSS = –5.0V±10%)
*7. The ratings when VSS = –3.0V are approximately 100% higher than when VSS = –5.0V.
*8. The input timing of the FR delay time is determined by the SED1522 (Slave).
The output timing of the FR delay time is determined by the SED1522 (Master).
SED1522
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