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参数资料
| 型号： | SFCA16GBH2BV4TO-I-QT-216-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 35/56页 |
| 文件大小： | 0K |
| 描述： | FLASH CFAST UDMA/MDMA/PIO 16GB |
| 标准包装： | 20 |
| 系列： | F-240 |
| 存储容量： | 16GB |
| 存储器类型： | 存储卡 - CFast? |
| 其它名称： | 1052-1099 |
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Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature
command is issued all data transfers shall occur on the low order D[7:0] data bus and the -IOIS16 signal shall
not be asserted for data register accesses. The host shall not enable this feature for DMA transfers.
Features 02h and 82h allow the host to enable or disable write cache in CFAST card that implement write cache.
When the subcommand disable write cache is issued, the CFAST card shall initiate the sequence to flush cache to
non-volatile memory before command completion.
Feature 03h allows the host to select the PIO or Multiword DMA transfer mode by specifying a value in the Sector
Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One
PIO mode shall be selected at all times. For Cards which support DMA, one DMA mode shall be selected at all
times. The host may change the selected modes by the Set Features command.
Table 53: Transfer Mode Values
Mode
PIO default mode
PIO default mode, disable IORDY
Bits (7:3)
00000b
00000b
Bits (2:0)
000b
001b
PIO flow control transfer mode
Reserved
Multi-Word DMA mode
Ultra DMA mode
Reserved
00001b
00010b
00100b
01000b
1000b
Mode
N/A
Mode
Mode
N/A
(1)
(1)
(1)
(1)Mode = transfer mode number
Notes: Multiword DMA is not permitted for devices configured in the PC Card Memory or the PC Card I/O interface
mode.
If a CFAST card supports PIO modes greater than 0 and receives a Set Features command with a Set Transfer Mode
parameter and a Sector Count register value of “00000000b”, it shall set its default PIO mode. If the value is
“00000001b” and the CFAST card supports disabling of IORDY, then the CFAST card shall set its default PIO mode
and disable IORDY. A CFAST card shall support all PIO modes below the highest mode supported, e.g., if PIO mode
is supported PIO mode 0 shall be supported.
Support of IORDY is mandatory when PIO mode 3 or above is the current mode of operation.
A CFAST card reporting support for Multiword DMA modes shall support all Multiword DMA modes below the
highest mode supported. For example, if Multiword DMA mode 2 support is reported, then modes 1 and 0 shall
also be supported. Note that Multiword DMA shall not be supported while PC Card interface modes are selected.
A CFAST card reporting support for Ultra DMA modes shall support all Ultra DMA modes below the highest mode
supported. For example, if Ultra DMA mode 2 support is reported then modes 1 and 0 shall also be supported.
If an Ultra DMA mode is enabled, any previously enabled Multiword DMA mode shall be disabled by the device.
If a Multiword DMA mode is enabled any previously enabled Ultra DMA mode shall be disabled by the device.
Feature 05h allows the host to enable Advanced Power Management. To enable Advanced Power Management,
the host writes the Sector Count register with the desired advanced power management level and then executes
a Set Features command with subcommand code 05h. The power management level is a scale from the lowest
power consumption setting of 01h to the maximum performance level of FEh.
Table 54shows these values.
Table 54: Advanced power management levels
Level
Maximum performance
Intermediate power management levels without Standby
Minimum power consumption without Standby
Intermediate power management levels with Standby
Minimum power consumption with Standby
Reserved
Reserved
Sector Count Value
FEh
81h-FDh
80h
02h-7Fh
01h
FFh
00h
In the current version the advanced power management levels are accepted, but don’t influe nce performance
and power consumption.
Device performance may increase with increasing power management levels. Device power consumption may
increase with increasing power management levels. The power management levels may contain discrete bands.
For example, a device may implement one power management method from 80h to A0h and a higher
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 0.92
CH-9552 Bronschhofen
Switzerland
F-240_data_sheet_CA-HxBV_Rev092.doc
Page 35 of 56
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