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参数资料
| 型号： | SFSD0512N1BN1TO-I-ME-151-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | FLASH MICRO SD 512MB IND TEMP |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 1 |
| 系列： | S-200u |
| 存储容量： | 512MB |
| 存储器类型： | 存储卡 - microSD? |
| 其它名称： | 1052-1060 |
7 Host access Specification
The following chapters summarize how the host accesses the card:
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Chapter 7.1 summarizes the SD and SPI buses.
Chapter 7.2 summarizes the registers.
7.1 SD and SPI Bus Modes
The card supports SD and the SPI Bus modes. Application can chose either one of the modes. Mode selection is
transparent to the host. The card automatically detects the mode of the reset command and will expect all further
communication to be in the same communication mode. The SD mode uses a 4-bit high performance data
transfer, and the SPI mode provides compatible interface to MMC host systems with little redesign, but with a
lower performance.
7.1.1 SD Bus Mode Protocol
The SD Bus mode has a single master (host) and multiple slaves (cards) synchronous topology. Clock, power, and
ground signals are common to all cards. After power up, the SD Bus mode uses DAT0 only; after initialization, the
host can change the cards’ bus width from 1 bit (DAT0) to 4 bits (DAT0 -DAT3). In high speed mode, only one card
can be connected to the bus.
Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and
terminated by a stop bit.
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Command: a command is a token which starts an operation. A command is sent from the host either to a
single card (addressed command) or to all connected cards (broadcast command). A command is
transferred serially on the CMD line.
Response: a response is a token which is sent from an addressed card, or (synchronously) from all
connected cards, to the host as an answer to a previously received command. A response is transferred
serially on the CMD line.
Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data
lines.
The SD bus signals are listed in Table 18, and the SD bus topology is illustrated in Figure 9: SD Bus Topology.
Table 18: SD Bus Signals
Signal
CLK
CMD
DAT0-DAT3
Vdd, Vss
Description
Host to card clock signal
Bidirectional Command/Response signal
4 Bidirectional data signals
Power and Ground
Figure 9: SD Bus Topology
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
info@swissbit.com
S-200u_data_sheet_SD-NxBN_Rev102
Page 12 of 23
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