参数资料
型号: SG5841SZ
厂商: Fairchild Semiconductor
文件页数: 10/15页
文件大小: 0K
描述: IC PWM FLYBACK ISOLATED CM 8-SOP
产品变化通告: Mold Compound Change 12/Dec/2007
标准包装: 2,500
输出隔离: 隔离
频率范围: 62kHz ~ 68kHz
输入电压: 11 V ~ 24.7 V
输出电压: 18V
工作温度: -20°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
Functional Description
Startup Current
Typical startup current is only 14μA, which allows a
high-resistance and low-wattage startup resistor to
minimize power loss. For an AC/DC adapter with
universal input range, a 1.5M ? , 0.25W startup resistor
and a 10μF/25V V DD hold-up capacitor are enough for
this application.
Operating Current
Operating current is around 4mA. The low operating
current enables better efficiency and reduces the
requirement of V DD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. Green mode dramatically reduces power
consumption under light-load and zero-load conditions.
Power supplies using a SG5841/J controller can meet
restrictive international regulations regarding standby
power consumption.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the SG5841/J
controller. This current is used to determine the center
PWM frequency. Increasing the resistance reduces
PWM frequency. Using a 26K ? resistor, R I , results in a
corresponding 65KHz PWM frequency. The relationship
between R I and the switching frequency is:
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16V and 10V. During startup, the hold-up capacitor
must be charged to 16V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply V DD before the energy can be delivered from
auxiliary winding of the main transformer. V DD must not
drop below 10V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply V DD during startup.
Gate Output / Soft Driving
The SG5841/J BiCMOS output stage is a fast totem-
pole gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect power MOSFET
transistors against undesirable gate over-voltage. A soft
driving waveform is implemented to minimize EMI.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability or prevents sub-harmonic oscillation. SG5841/J
f PWM
=
1690
R I (K Ω )
(KHz)
(1)
inserts a synchronized, positive-going ramp at every
switching cycle.
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5841J also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency-hopping function helps reduce EMI emission
of a power supply with minimum line filters.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized in to regulate
output voltage and provide pulse-by-pulse current
limiting. The switch current is detected by a sense
resistor into the SENSE pin. The PWM duty cycle is
determined by this current-sense signal and the
feedback voltage. When the voltage on the SENSE pin
reaches around V COMP = (V FB –1.0)/3.2, a switch cycle is
terminated immediately. V COMP is internally clamped to a
variable voltage around 0.85V for output power limit.
? 2006 Fairchild Semiconductor Corporation
SG5841J ? Rev. 1.3.5
10
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
R S , reaches the threshold voltage, around 0.85V, the
output GATE drive is turned off after delay, t PD . This
delay introduces additional current, proportional to t PD ?
V IN / L P . The delay is nearly constant, regardless of the
input voltage V IN . Higher input voltage results in larger
additional current and the output power limit is higher
than under low-input line voltage. To compensate this
variation for a wide AC input range, a sawtooth power-
limiter (saw limiter) is designed to solve the unequal
power-limit problem. The saw limiter is designed as a
positive ramp signal (V limit_ramp ) and fed to the inverting
input of the OCP comparator. This results in a lower
current limit at high-line inputs than at low-line inputs.
V DD Over-Voltage Clamping
V DD over-voltage clamping prevents damage due to
abnormal conditions. If V DD voltage is over the V DD over-
voltage clamping voltage (V DD-CLAMP ) and lasts for t D-
VDDCLAMP , the PWM pulses are disabled until the V DD
drops below the V DD over-voltage clamping voltage.
www.fairchildsemi.com
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