参数资料
型号: SI1902DL-T1-E3
厂商: Vishay Siliconix
文件页数: 6/9页
文件大小: 0K
描述: MOSFET N-CH DUAL 20V SC70-6
产品目录绘图: DL-T1-E3 Series SOT-363
标准包装: 1
系列: TrenchFET®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 660mA
开态Rds(最大)@ Id, Vgs @ 25° C: 385 毫欧 @ 660ma,4.5V
Id 时的 Vgs(th)(最大): 1.5V @ 250µA
闸电荷(Qg) @ Vgs: 1.2nC @ 4.5V
功率 - 最大: 270mW
安装类型: 表面贴装
封装/外壳: 6-TSSOP,SC-88,SOT-363
供应商设备封装: SC-70-6
包装: 标准包装
产品目录页面: 1663 (CN2011-ZH PDF)
其它名称: SI1902DL-T1-E3DKR
AN814
Vishay Siliconix
Dual-Channel LITTLE FOOT R SC-70 6-Pin MOSFET
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
This technical note discusses the pin-outs, package outlines,
pad patterns, evaluation board layout, and thermal
performance for dual-channel LITTLE FOOT power
MOSFETs in the SC-70 package. These new Vishay Siliconix
devices are intended for small-signal applications where a
miniaturized package is needed and low levels of current
(around 250 mA) need to be switched, either directly or by
using a level shift configuration. Vishay provides these devices
with a range of on-resistance specifications in 6-pin versions.
The new 6-pin SC-70 package enables improved
on-resistance values and enhanced thermal performance.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
SOT-363
SC-70 (6-LEADS)
applications for which this package is intended. For the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 20% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB).
EVALUATION BOARDS FOR THE DUAL
SC70-6
The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches
by 0.5 inches. The copper pad traces are the same as
described in the previous section, Basic Pad Patterns . The
board allows interrogation from the outer pins to 6-pin DIP
connections permitting test sockets to be used in evaluation
testing.
The thermal performance of the dual SC-70 has been
measured on the EVB with the results shown below. The
minimum recommended footprint on the evaluation board was
compared with the industry standard 1-inch square FR4 PCB
with copper on both sides of the board.
S 1
1
6
D 1
THERMAL PERFORMANCE
G 1
2
5
G 2
D 2
3
4
S 2
Junction-to-Foot Thermal Resistance
(the Package Performance)
Top View
FIGURE 1.
For package dimensions see outline drawing SC-70 (6-Leads)
( http://www.vishay.com/doc?71154 )
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFET s, ( http://www.vishay.com/doc?72286 ) for the 6-pin
SC-70. This basic pad pattern is sufficient for the low-power
Document Number: 71237
12-Dec-03
Thermal performance for the dual SC-70 6-pin package
measured as junction-to-foot thermal resistance is 300 _ C/W
typical, 350 _ C/W maximum. The “foot” is the drain lead of the
device as it connects with the body. Note that these numbers
are somewhat higher than other LITTLE FOOT devices due to
the limited thermal performance of the Alloy 42 lead-frame
compared with a standard copper lead-frame.
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
The typical R θ JA for the dual 6-pin SC-70 is 400 _ C/W steady
state. Maximum ratings are 460 _ C/W for the dual. All figures
based on the 1-inch square FR4 test board. The following
example shows how the thermal resistance impacts power
dissipation for the dual 6-pin SC-70 package at two different
ambient temperatures.
www.vishay.com
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