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| 型号： | SI3062-F-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/62页 |
| 文件大小： | 0K |
| 描述： | IC DAA ENH FCC LINE-SIDE 16SOIC |
| 标准包装： | 48 |
| 功能： | 直接存取装置（DAA） |
| 电路数： | 1 |
| 电流 - 电源： | 9mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
| 包括： | 结帐音调检测，线路电压监视器，回路电流监视器，过载检测，振铃检测器 |
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Si306x
18
Rev. 0.9
host provides a digital test waveform on SDI. This data
passes across the isolation barrier, is transmitted to and
received from the line, passes back across the isolation
barrier, and is presented to the host on SDO. To enable
this mode, clear the HBE bit (Register 2, bit 1).
When the HBE bit is cleared, this causes a dc offset that
affects the signal swing of the transmit signal. Silicon
Labs recommends that the transmit signal be 12 dB
lower than normal transmit levels. A lower level
eliminates clipping from the dc offset that results from
disabling the hybrid. It is assumed in this test that the
line ac impedance is nominally 600
.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
6.8. Exception Handling
The Si306x provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling
systems can read several status bits. The bit of highest
importance is the frame detect bit (FDT, Register 12,
bit 6), which indicates that the system-side (Si306x) and
line-side devices are communicating. During normal
operation, the FDT bit can be checked before reading
bits for information about the line-side. If FDT is not set,
the following bits related to the line-side are invalid—
RDT, RDTN, RDTP, LCS[4:0], LSID[1:0], REVB[3:0],
LCS2[7:0], LVS[7:0], ROV, BTD, DOD, and OVL; the
RGDT operation is also non-functional.
Following Powerup and reset, the FDT bit is not set
because the PDL bit (Register 6 bit 4) defaults to 1. The
communications link does not operate and no
information about the line-side can be determined. The
user must program the clock generator to a valid
configuration for the system and clear the PDL bit to
activate the communications link. As the system- and
line-side devices are establishing communication, the
system-side device does not generate FSYNC signals.
Establishing communication takes less than 10 ms.
Therefore, if the controlling DSP serial interface is
interrupt driven based on the FSYNC signal, the
controlling DSP does not require a special delay loop to
wait for this event to complete.
The FDT bit also can indicate if the line-side device
executes an off-hook request successfully. If the line-
side device is not connected to a phone line, the FDT bit
remains cleared. The controlling DSP must provide
sufficient time for the line-side to execute the off-hook
request. The maximum time for FDT to be valid
following an off-hook request is 10 ms. If the FDT bit is
high, the LCS[4:0] bits indicate the amount of loop
current flowing. If the FDT fails to be set following an off-
hook request, the PDL bit (Register 6) must be set high
for at least 1 ms to reset the line-side.
6.9. Revision Identification
With the Si306x the system designer can determine the
revision of the system-side module and/or the line-side
device. The REVA[3:0] bits (Register 11, bits 3:0)
identify the revision of the system-side module. The
REVB[3:0] bits (Register 13, bits 3:0) identify the
revision of the line-side device. Table 8 lists revision
values for all devices and might contain future revisions
not yet in existence.
6.10. Parallel Handset Detection
The Si306x can detect a parallel handset going off-
hook. When the Si306x is off-hook, the loop current can
be monitored with the LCS or LCS2 bits. A significant
drop in loop current signals a parallel handset going off-
hook. If a parallel handset going off-hook causes the
loop current to drop to 0, the LCS and LCS2 bits will
read all 0s. Additionally, the Drop-Out Detect (DOD) bit
will fire (and generate an interrupt if the DODM bit is set)
indicating that the line-derived power supply has
collapsed.
If the Si3062 or Si3063 line-side device is used, the LVS
bits also can be read when on- or off-hook to determine
the line voltage. Significant drops in line voltage can
signal a parallel handset. For the Si306x to operate in
parallel with another handset, the parallel handset must
have a sufficiently high dc termination to support two off-
hook DAAs on the same line. Improved parallel handset
operation can be achieved by changing the dc
impedance from 50
to 800 and reducing the DCT
pin voltage with the DCV[1:0] bits.
6.11. Line Voltage/Loop Current Sensing
The Si306x line-side devices can measure loop current.
The 5-bit LCS[4:0] register reports loop current
measurements when off-hook. The Si3062, Si3063, and
Si3065 offer an additional register to report loop current
to a finer resolution (LCS2[7:0]). The Si3062, Si3063,
and Si3065 also offer the capability to measure line
voltage. The LVS[7:0] register monitors voltage both on
Table 8. Revision Values
Revision
Si306x
C
0011
D0100
E0101
F0110
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3062-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
| SI3062-X-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3063 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| Si3063-F-FS | 功能描述:电信线路管理 IC Enhanced V.92 Global Line-Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3063-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
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