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| 型号： | SI3062-F-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 16/62页 |
| 文件大小： | 0K |
| 描述： | IC DAA ENH FCC LINE-SIDE 16SOIC |
| 标准包装： | 48 |
| 功能： | 直接存取装置（DAA） |
| 电路数： | 1 |
| 电流 - 电源： | 9mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
| 包括： | 结帐音调检测，线路电压监视器，回路电流监视器，过载检测，振铃检测器 |
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Si306x
Rev. 0.9
23
ignored. Ring validation can be enabled during normal
operation and in low power sleep mode. The external
MCLK signal is required in low power sleep mode for
ring validation.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
Ring validation requires five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal on the RAS[5:0] bits
(Register 24). The frequency is measured by
calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency on the RMX[5:0] bits (Register 22).
Time interval over which the ring signal must be the
correct frequency on the RCC[2:0] bits (Register 23).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
accommodate distinctive ringing.
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in normal operating mode and
low-power sleep mode.
6.19. Ringer Impedance and Threshold
The ring detector in many DAAs is ac coupled to the line
with a large 1 F, 250 V decoupling capacitor. The ring
detector on the Si306x DAA is resistively coupled to the
line. This coupling produces a high ringer impedance to
the line of approximately 20 M
to meet the majority of
country PTT specifications, including FCC and TBR21.
Several countries including Poland, South Africa, and
Slovenia, require a maximum ringer impedance that can
be met with an internally synthesized impedance by
setting the RZ bit (Register 16, bit 1).
Some
countries
also
specify
ringer
thresholds
differently. The RT bit (Register 16, bit 0) selects
between two different ringer thresholds: 15 V ±10% and
21.5 V ±10%. These two settings satisfy ringer
threshold requirements worldwide. The thresholds are
set so that a ring signal is guaranteed to not be detected
below the minimum, and a ring signal is guaranteed to
be detected above the maximum.
6.20. Pulse Dialing and Spark Quenching
Pulse dialing results from going off- and on-hook to
generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity that include make and
break times, make resistance, and rise and fall times. In
a traditional solid-state dc holding circuit, there are
many problems in meeting these requirements.
The Si306x dc holding circuit actively controls the on-
hook and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries such as
Italy, the Netherlands, South Africa, and Australia deal
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional solution to
the problem is to put a parallel resistive capacitor (RC)
shunt across the hookswitch relay. However, the
capacitor required is large (~1F, 250V) and relatively
expensive. In the Si306x, loop current can be controlled
to achieve three distinct on-hook speeds to pass spark
quenching tests without additional BOM components.
Through the settings of four bits in three registers, OHS
(Register 16), OHS2 (Register 31), SQ1 and SQ0
(Register 59), a slow ramp down of loop current can be
achieved which induces a delay between the time OH
bit is cleared and the time the DAA actually goes on-
hook.
To ensure proper operation of the DAA during pulse
dialing, disable the automatic resistor calibration that is
performed each time the DAA enters the off-hook state
by setting the RCALD bit (Register 25, bit 5).
6.21. Billing Tone Detection and Receive
Overload
“Billing tones” or “metering pulses” generated by the
Central Office can cause modem connection difficulties.
The billing tone is typically either a 12 or 16 kHz signal
and is sometimes used in Germany, Switzerland, and
South Africa. Depending on line conditions, the billing
tone might be large enough to cause major errors in the
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3062-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
| SI3062-X-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3063 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| Si3063-F-FS | 功能描述:电信线路管理 IC Enhanced V.92 Global Line-Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3063-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
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