参数资料
型号: SI3460-E02-GMR
厂商: Silicon Laboratories Inc
文件页数: 14/24页
文件大小: 0K
描述: IC POWER MANAGEMENT CTLR 11VQFN
标准包装: 500
应用: 供电设备(PSE)
电流 - 电源: 500mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-VFDFN 裸露焊盘
供应商设备封装: 11-QFN(3x3)
包装: 带卷 (TR)
Si3460
5. Design Considerations
5.1. Isolation
The Si3460-EVB's PSE output power at V OUT is not isolated from the input power source (V IN ). Isolation of PSE
output power requires that the input be isolated from earth ground. Typically, an ac to dc power supply or "wall
wart" is used to provide the 12 V power so the output of this supply is isolated from earth ground.
5.2. External Component Selection
Detailed notes on external component selection are provided in the Si3460-EVB User's Guide schematics and
BOM. In general, these recommendations must be followed closely to ensure output power stability and ripple
(power stage components), surge protection (surge protection diode), and overall IEEE 802.3 compliance.
5.3. Input DC Supply
The input power supply should be rated for at least 25% higher power level than the output power level chosen.
This is primarily to account for the 75 to 80% nominal efficiency performance of the Si3460-EVB reference design.
For example, to support a Class 0 PSE, for example, the input supply should be capable of supplying 19.25 W
(15.4 W x 1.25 = 19.25 W).
5.4. STATUS and RESET Interface
To reference the RESET and STATUS pins to system ground, the level shifting method shown in Figure 3 can be
used. Refer to the schematic in the Si3460-EVB document.
+12V
R8
(66.5 k ? )
U1
R22
(1 k ? )
Shunt
Regulator
TLV431
Si3460
VDD
STATUS
RST
R40
(332 ? )
R7
(40.2 k ? )
1 uF/
+8.7V
6.3 V
RST CONTROL
Status
Output
R*3.3/2.7
405 ?
806 ?
System Gnd
Figure 3. STATUS and RESET Pin Interface when Referenced to System Ground
14
Rev. 1.2
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