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| 型号： | SI5013-D-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 13/26页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 标准包装： | 60 |
| 系列： | DSPLL® |
| 类型： | 时钟和数据恢复（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 应用 |
| 输入： | 时钟 |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 675MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-MLP-EP（5x5） |
| 包装： | 管件 |
| 其它名称： | 336-1277 |
Si5013
20
Rev. 1.6
5
6
REFCLK+
REFCLK–
ISee Table 2
Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 7 on page 12 for typical reference clock
frequencies.
7
LOL
OLVTTL
Loss-of-Lock.
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
8
LTR
ILVTTL
Lock-to-Reference.
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock locks to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
9
LOS
OLVTTL
Loss-of-Signal.
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
10
DSQLCH
LVTTL
Data Squelch.
When driven high, this pin forces the data present
on DOUT+ to zero and DOUT– to one. For normal
operation, this pin should be low. DSQLCH may be
used during LOS/LOL conditions to prevent random
data from being presented to the system.
Note: This input has a weak internal pulldown.
11,14,18,21,
25
VDD
3.3 V
Supply Voltage.
Nominally 3.3 V.
12
13
DIN+
DIN–
ISee Table 2
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is recom-
mended.
15
GND
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
Table 8. Si5013 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5013-D-GMR | 功能描述:时钟发生器及支持产品 OC-3/12 STM-1/4 Sonet/SDH CDR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5013-EVB | 功能描述:时钟和定时器开发工具 SNT/SDH OC3/12 STM1/ w/limit amp 3.3V RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| SI5013-X-GM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| SI-50141-F | 功能描述:CONN MAGJACK 1PT 10/100BTX G/Y RoHS:是 类别:连接器，互连式 >> 模块 - 带磁性元件的插座 系列:MagJack® ST SI-50000 标准包装:63 系列:Mag45 连接器类型:RJ45 端口数:1 行数:1 安装类型:面板安装，通孔，直角 速度:10/100 Base-T 板上方高度:0.555"（14.10mm） LED 颜色:绿 - 绿 每一插座芯体的数目:5 屏蔽:屏蔽 翼片方向:上 特点:板锁 包装:托盘 |
| SI-50142 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-50142 |
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