参数资料
型号: SI51219-A01AFT
厂商: Silicon Laboratories Inc
文件页数: 11/12页
文件大小: 0K
描述: IC CLK GEN FACTORY CONFIG 8TSSOP
标准包装: 100
类型: *
PLL: 带旁路
输入: 时钟,晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:3
差分 - 输入:输出: 无/无
频率 - 最大: 200MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.63 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
Si51219
8
Preliminary Rev. 0.7
4. Pin Descriptions: 8-Pin TSSOP
Table 5. Si51219 Pin Descriptions
Pin #
Name
Type
Description
1
VDD
PWR 2.5 to 3.3 V power supply.
2
XOUT
O
Crystal output. Leave this pin unconnected (floating) if an external clock
input is used.
3
XIN/CLKIN
I
External crystal and clock input.
4
SSCLK1/REFCLK/
FSEL/SSEL/SSON/
OE2
I/O
Programmable SSCLK1 or REFCLK output or MultiFunction control
input. The frequency at this pin is synthesized by internal PLL if pro-
grammed as SSCLK1 with or without spread. If programmed as REF-
CLK, output clock is buffered output of crystal or reference clock input. If
programmed as MultiFunction control input, it can be OE, FSEL, SSEL
and SSON.
5
VSS
GND Ground.
6
SSCLK2/REFCLK_D/
OE1/FSEL/SSEL/
SSON/PD
I/O
Programmable SSCLK2 or REFCLK_D output or MultiFunction control
input. The frequency at this pin is synthesized by internal PLL if pro-
grammed as SSCLK2 with or without spread. If programmed as
REFCLK_D, output clock is buffered output of crystal or reference clock
input divided by 2 to 32. If programmed as MultiFunction control input, it
can be OE, PD, FSEL, SSEL and SSON.
7
SSCLK3
O
Programmable SSCLK3 output. The frequency at this pin is synthesized
by internal PLL with or without spread. It is power by VDDO pin (pin 8).
8
VDDO
PWR 1.8 to 3.3 V output power supply to SSCLK3 (pin 7) VDDO VDD.
8
Si51219
7
6
5
4
1
2
3
VDDO
SSCLK3
SSCLK2/REFCLK_D
FSEL/SSEL/
SSON/PD/OE1
VSS
SSCLK1/REFCLK
FSEL/SSEL/SSON/
OE2
XIN/CLKIN
XOUT
VDD
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