参数资料
型号: SI51219-A01AFT
厂商: Silicon Laboratories Inc
文件页数: 9/12页
文件大小: 0K
描述: IC CLK GEN FACTORY CONFIG 8TSSOP
标准包装: 100
类型: *
PLL: 带旁路
输入: 时钟,晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:3
差分 - 输入:输出: 无/无
频率 - 最大: 200MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.63 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
Si51219
6
Preliminary Rev. 0.7
2. Design Considerations
2.1. Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 μF must be used between VDD and VSS on the pins 1 and
8. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin. In addition, a 10 F capacitor should be placed between VDD and VSS.
Series Termination Resistor
: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 inch. The nominal impedance of the SSCLK output is about
30 . Use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as
close to the SSCLK output as possible.
Crystal and Crystal Load:
Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone
crystals
. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula;
C1 = C2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the Si51219 pin capacitance (4 pF)
Cp is the parasitic capacitance of the PCB traces.
Example
: If a crystal with CL=12 pF specification is used and Cp=1 pF (parasitic PCB capacitance on PCB), 19 or 20 pF
external capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp value.
VDD
VDDO
XOUT
XIN
FSEL
VSS
SSCLK2
SSCLK3
VDD
Si51219
0.1F
10F
CL1
CL2
VDD
5K
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