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参数资料
| 型号： | SI5316-B-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/26页 |
| 文件大小： | 0K |
| 描述： | IC PREC JITTER ATTENUATOR 36QFN |
| 标准包装： | 50 |
| 系列： | DSPLL® |
| 类型： | 时钟振动衰减器 |
| PLL： | 带旁路 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 710MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 管件 |
Si5316
18
Rev. 1.0
21
CS
I
LVCMOS
Input Clock Select.
This pin functions as the input clock selector. This input is internally
deglitched to prevent inadvertent clock switching during changes in
the CKSEL input state.
0 = Select CKIN1
1 = Select CKIN2
Must be driven high or low.
23
22
BWSEL1
BWSEL0
I
3-Level*
Bandwidth Select.
Three level inputs that select the DSPLL closed loop bandwidth.
Detailed operations and timing characteristics for these pins may be
found in the Any-Frequency Precision Clock Family Reference Man-
ual.
These pins are both pull-ups and pull-downs and default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
25
24
FRQSEL
1
FRQSEL
0
I
3-Level*
Frequency Select.
Sets the output frequency of the device. When the frequency of
CKIN1 is not equal to CKIN2, the lower frequency input clock must
be equal to the output clock frequency. These pins have both weak
pull-ups and weak pull-downs and default to M. For the pin settings,
see Table 3 on page 8.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
26
CK1DIV
I
3-Level*
Input Clock 1 Pre-Divider Select.
Pre-divider on CKIN1. Used with CK2DIV to divide input clock
frequencies to a common value.
L = CKIN1 input divider set to 1.
M = CKIN1 input divider set to 4.
H = CKIN1 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
27
CK2DIV
I
3-Level*
Input Clock 2 Pre-Divider Select.
Pre-divider on CKIN2. Used with CK1DIV to divide input clock
frequencies to a common value.
L = CKIN2 input divider set to 1.
M = CKIN2 input divider set to 4.
H = CKIN2 input divider set to 32.
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Table 8. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5316-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PRECISION CLOCK JITTER ATTENUATOR, 1 OUTPUT - Tape and Reel |
| Si5316-C-GM | 功能描述:锁相环 - PLL Precsn Clock Jittr Attenuatr 1 Output RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5316-C-GMR | 功能描述:时钟发生器及支持产品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5316-EVB | 功能描述:时钟和定时器开发工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| SI5317 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
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