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| 型号： | SI5316-B-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 7/26页 |
| 文件大小： | 0K |
| 描述： | IC PREC JITTER ATTENUATOR 36QFN |
| 标准包装： | 50 |
| 系列： | DSPLL® |
| 类型： | 时钟振动衰减器 |
| PLL： | 带旁路 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 710MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 管件 |
Si5316
Rev. 1.0
15
4. Functional Description
The Si5316 is a precision jitter attenuator for high-speed
communication systems, including OC-48/STM-16, OC-
192/STM-64, 10G Ethernet, and 10G Fibre Channel.
The Si5316 accepts dual clock inputs in the 19, 38, 77,
155, 311, or 622 MHz frequency range and generates a
jitter-attenuated clock output at the same frequency.
Within each of these clock ranges, the device can be
tuned approximately 15% higher than nominal SONET/
SDH frequencies, up to a maximum of 710 MHz in the
622 MHz range. The Si5316 is based on Silicon
Laboratories' 3rd-generation DSPLL technology, which
provides any-frequency synthesis and jitter attenuation
in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. For
applications which require input clocks at different
frequencies, the frequency of CKIN1 can be 1x, 4x, or
32x the frequency of CKIN2 as specified by the CK1DIV
and CK2DIV inputs.
The Si5316 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 100 Hz to
7.9 kHz. To calculate potential loop bandwidth values
for a given input/output clock
frequency, Silicon
Laboratories
offers
a
PC-based
software
utility,
DSPLLsim, that calculates valid loop bandwidth settings
automatically. This utility can be downloaded from http://
www.silabs.com/timing.
The
Si5316
supports
manual
active
input
clock
selection. The Si5316 monitors both input clocks for
loss-of-signal and provides a LOS alarm when it detects
missing pulses on either input clock. Hitless switching is
not supported by the Si5316. During a clock transition,
the phase of the output clock will slew at a rate defined
by the PLL loop bandwidth until the original input clock
phase to output clock phase is restored. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase
of the input clock in relation to the phase of the
feedback clock.
The Si5316 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
4.1. External Reference
An
external,
38.88 MHz
clock
or
a
low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within
the
DSPLL. This
external reference is required for the device to operate.
Silicon Laboratories recommends using a high quality
crystal. Specific recommendations may be found in the
Family Reference Manual. An external 38.88 MHz clock
from a high quality OCXO or TCXO can also be used as
a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
4.2. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5316. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5316-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PRECISION CLOCK JITTER ATTENUATOR, 1 OUTPUT - Tape and Reel |
| Si5316-C-GM | 功能描述:锁相环 - PLL Precsn Clock Jittr Attenuatr 1 Output RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5316-C-GMR | 功能描述:时钟发生器及支持产品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5316-EVB | 功能描述:时钟和定时器开发工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| SI5317 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
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