参数资料
| 型号： | SI5320-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI5320 |
| 标准包装： | 1 |
| 系列： | DSPLL® |
| 主要目的： | 计时，时钟发生器 |
| 已用 IC / 零件： | SI5320 |
| 已供物品： | 板 |
| 其它名称： | 336-1142 |
Si 5320- EV B
Functional Overview
The Si5320-EVB is the customer evaluation board for
the Si5320 SONET/SDH Precision Port Card Clock IC.
It is supplied to customers for evaluation of the Si5320
device. The board provides access to signals
associated with normal operation of the device and
signals that are reserved for factory testing purposes.
Power Supply Selection and Connections
The Si5320-EVB board is switch selectable for
operation using either a single 3.3 V or a single 2.5 V
supply.
For operation using a 3.3 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J3.
2. Remove the connection between VDD33 and VDD25 by
removing the jumper on header JPI.
3. Set VSEL33 high by sliding the switch on the VSEL33
(JP6) to the side marked “1”.
4. Connect the power supply ground lead and 3.3 V supply
lead to the GND and VDD terminals of the board’s power
connector, J3.
For operation using a 2.5 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J3.
2. Set VSEL33 low by sliding the switch on the VSEL33 (JP6)
to the side marked “0”.
3. Connect VDD33 and VDD25 by installing a jumper
between one of the 3.3 V pins and one of the 2.5 V pins on
header JPI.
4. Connect the power supply ground lead and 2.5 V supply
lead to the GND and VDD terminals of the board’s power
connector, J3.
Power Consumption
Typical supply current draw for the Si5320-EVB is
110 mA.
Si5320 Control Inputs
The control inputs to the Si5320 are each routed from
the center pin of a SPDT switch, JP5, to the Si5320
device. Additionally, the switches at JP5 are connected
to GND on one side of the switch and to VDD33 on the
other side. This arrangement allows easy configuration
of each input to either a high or low state. To further
reduce the coupling of noise into the device through
these control inputs, the signals are routed on internal
layers between ground planes.
RSTN/CAL Settings for Normal Operation
and Self-Calibration
The RSTN/CAL signal is an LVTTL input to the Si5320
and has an on-chip pulldown mechanism. This pin must
be set high for normal operation of the Si5320 device.
Setting RSTN/CAL low forces the Si5320 into the reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence.
The Si5320 device initiates self-calibration at powerup if
the RSTN/CAL signal is held high. A self-calibration of
the device also can be manually initiated by
momentarily pushing the RSTN/CAL switch, SWI and
then releasing.
Manually initiate self-calibration after changing the state
of either the BWSEL[1:0] control inputs or the FEC[1:0]
inputs.
Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires a valid
input clock. If the self-calibration is initiated without a
valid clock present, the device waits for a valid clock
before completing the self-calibration. The Si5320 clock
output is set to the lower end of the operating frequency
range while the device waits for a valid clock. After the
clock input is validated, the calibration process runs to
completion, the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.
Status Signals
The status outputs from the Si5320 device are each
routed to one pin of a two-row header. The signals are
arranged so that each signal has a ground pin adjacent
to the signal pin for reference. The row of signal pins is
marked with an “S”, and the row of ground pins is
marked with a “G”.
Visible indicators are added to the LOS and CAL_ACTV
signals. The LEDs glow when the signal is active and
the LED enable switch is set to ON. The LOS LED is
illuminated when the device does not recognize a valid
clock input. The CAL_ACTV LED is illuminated when
the device is calibrating to an input clock.
Differential Clock Input Signals
The differential Clock inputs to the Si5320-EVB board
are ac coupled and terminated on the board at a
location near the SMA input connectors. The
termination components are located on the top side of
the board. The termination circuit consists of two 50 ?
2
Preliminary Rev. 0.4
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5320-F-BC | 功能描述:时钟合成器/抖动清除器 USE 634-SI5320-G-BC RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5320-F-XC4 | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5320-G-BC | 功能描述:时钟发生器及支持产品 SONET/SDH Precision Clock 19 155 622MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5320-H-BL | 功能描述:时钟发生器及支持产品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5320-H-GL | 功能描述:时钟发生器及支持产品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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