参数资料
| 型号： | SI5320-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 3/18页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI5320 |
| 标准包装： | 1 |
| 系列： | DSPLL® |
| 主要目的： | 计时，时钟发生器 |
| 已用 IC / 零件： | SI5320 |
| 已供物品： | 板 |
| 其它名称： | 336-1142 |
Si5320-EVB
and a 0.1 μ F capacitor, such that the positive and
negative inputs of the differential pair each see a 50 ?
termination to “ac ground,” and the line-to-line
termination impedance is 100 ? .
For single-ended operation, supply a signal to one of
the differential inputs (usually the positive input). The
other input should be shorted to ground using an SMA
shorting plug. The on-board termination circuit provides
a 50 ? termination to ac-ground for each leg of the
differential pair.
Differential Clock Output Signals
The differential clock outputs from the Si5320 device
are routed to the perimeter of the circuit board using
50 ? transmission line structures. The capacitors that
provide ac-coupling are located near the clock output
SMA connectors.
Internal Regulator Compensation
The Si5320-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0 ? resistor. The
capacitor pads are populated with a low ESR 33 μ F
tantalum capacitor. This is the suggested compensation
circuit for Si5320 devices.
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
The acceptable range for the time constant at this node
is 15 μ s to 50 μ s. The capacitor used on the board is a
33 μ F capacitor with an ESR of .8 ? . This yields a time
constant of 26.4 μ s. The designer could decide to use a
330 μ F capacitor with an ESR of .15 ? . This yields a
time constant of 49.5 μ s. Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330 μ F case provides greater
noise filtering. However, the large case size of the
330 μ F capacitor might make it impractical for many
applications. The Si5320 device is specified with the
33 μ F cap.
Default Jumper Settings
The default jumper settings for the Si5320-EVB board
are given in Table 1. These settings configure the board
for operation from a 3.3 V supply.
Table 1. Si5320-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
JP6
JP1
JP5
JP7
Signal
VSEL33
VDD33
VALTIME
FEC[0]
FEC[1]
BWSEL[0]
BWSEL[1]
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
FRQSEL[0]
FRQSEL[1]
DBLBW
FXDDELAY
LED ENABLE
State
1
Open
0
0
0
0
1
1
0
0
1
1
1
0
On
Notes
Internal Regulator enabled
3.3 V plane not connected to 2.5 V plane
100 ms Validation Time
No FEC scaling
No FEC scaling
Loop Filter Bandwidth = 800 Hz
Loop Filter Bandwidth = 800 Hz
Clock IN = 19.44 MHz
Clock IN = 19.44 MHz
Clock IN = 19.44 MHz
Clock Out = 622.08 MHz
Clock Out = 622.08 MHz
Selected bandwidth not doubled
Fixed Delay disabled
LED Indicators enabled
Preliminary Rev. 0.4
3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5320-F-BC | 功能描述:时钟合成器/抖动清除器 USE 634-SI5320-G-BC RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| SI5320-F-XC4 | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5320-G-BC | 功能描述:时钟发生器及支持产品 SONET/SDH Precision Clock 19 155 622MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5320-H-BL | 功能描述:时钟发生器及支持产品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5320-H-GL | 功能描述:时钟发生器及支持产品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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