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| 型号： | SI5322-C-GM |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 1/24页 |
| 文件大小： | 0K |
| 描述： | IC PREC CLOCK MULTIPLIER 36-QFN |
| 标准包装： | 490 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CML，CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 无/是 |
| 电源电压： | 1.71 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN（6x6） |
| 包装： | 托盘 |
Rev. 0.51 2/12
Copyright 2012 by Silicon Laboratories
Si5322
P IN-P ROGRAMMABLE P RECISION C LOCK M ULTIPLIER
Features
Applications
Description
The Si5322 is a low jitter, precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and
Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44
to 707 MHz and generates two equal frequency-multiplied clock outputs
ranging from 19.44 to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET,
Ethernet, and Fibre Channel rates. The Si5322 is based on Silicon
Laboratories' 3rd-generation DSPLL technology, which provides any-
frequency synthesis in a highly-integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop
bandwidth
is
digitally
programmable,
providing
jitter
performance
optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5322 is ideal for providing clock multiplication in high
performance timing applications.
Not recommended for new
designs. For alternatives, see the
Si533x family of products.
Selectable output frequencies
ranging from 19.44 to 1050 MHz
Low jitter clock outputs with jitter
generation as low as 0.6 psRMS
(50kHz–80MHz)
Integrated loop filter with
selectable loop bandwidth
(150 kHz to 1.3 MHz)
Dual clock inputs with manual or
automatically controlled
switching
Dual clock outputs with
selectable signal format:
LVPECL, LVDS, CML, CMOS
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOS alarm output
Pin-programmable settings
On-chip voltage regulator for
1.8 V ±5%, 2.5 or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead
QFN
Pb-free, RoHS compliant
SONET/SDH OC-48/STM-16
and OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line
cards
ITU G.709 line cards
Optical modules
Test and measurement
Ordering Information:
See page 18.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
FRQTBL
AUTOSEL
RST
C2B
C1B
GND
VDD
GND
VDD
CKIN2+
CKIN2–
DB
L2
_B
Y
VDD
CKIN1+
CKIN1–
CS_CA
BWSEL0
BWSEL1
FRQSEL1
FRQSEL2
FRQSEL3
CKOUT
1
–
SFO
U
T
1
GND
VDD
SF
O
U
T0
CKOUT
2
–
CKOUT
2
+
NC
GND
Pad
FRQSEL0
GND
9
18
19
28
NC
GND
CKOUT
1
+
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5322-C-GMR | 功能描述:时钟发生器及支持产品 Pin-Ctrl Precision Clk Xplier 2/2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5323 | 制造商:SILABS 制造商全称:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5323-B-GM | 功能描述:锁相环 - PLL PIN-PROGRAMMABLE CLK MULT / JITTER ATTEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| SI5323-B-GMR | 制造商:Silicon Laboratories Inc 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATO - Tape and Reel |
| Si5323-C-GM | 功能描述:锁相环 - PLL PIN-PROGRAMMABLE CLK MULT / JITTER ATTEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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