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参数资料
| 型号： | SI5327D-C-GMR |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 243 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC36 |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36 |
| 文件页数： | 46/60页 |
| 文件大小： | 715K |
| 代理商： | SI5327D-C-GMR |
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Si5327
50
Preliminary Rev. 0.4
4
LOS2
O
LVCMOS
CKIN2 Invalid Indicator.
This pin functions as a LOS alarm indicator for CKIN2 if
CK2_BAD_PIN
=1.
0 = CKIN2 present
1 = LOS on CKIN2
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN
= 0, the pin tristates.
5, 10, 32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following VDD pins:
50.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to the device as is practical.
7
6
XB
XA
IAnalog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Si53xx Family Reference
Manual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Accepts
37–41 MHz crystal or reference clock, as determine by the RATE
pin setting.
8, 15, 31
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
RATE
I
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects an external crystal or reference clock
to be applied to the XA/XB interface.
L setting (GND) = crystal on XA/XB
M setting (VDD/2) = clock or XO on XA/XB
H setting (VDD) = reserved
Some designs may require an external resistor voltage divider when
driven by an active device that will tristate.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
13
CKIN2+
CKIN2–
IMulti
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Pin #
Pin Name
I/O
Signal Level
Description
Note:
Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
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| SI5334C-A00153-GM | PLL BASED CLOCK DRIVER, QCC24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5327-EVB | 功能描述:时钟和定时器开发工具 SI5327 EVAL BOARD RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| SI5328 | 制造商:SILABS 制造商全称:SILABS 功能描述:ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER |
| SI5328B-C-GM | 制造商:Silicon Laboratories Inc 功能描述:G.8262 SYNCE CLOCK MULTIPLIER/JITTER ATTENUATOR - Trays 制造商:Silicon Laboratories Inc 功能描述:IC CLK MULTIPLIER ETH 36QFN |
| SI5328B-C-GMR | 制造商:Silicon Laboratories Inc 功能描述:IC CLK MULTIPLIER ETH 36QFN |
| SI5328C-C-GM | 制造商:Silicon Laboratories Inc 功能描述:G.8262 SYNCE CLOCK MULTIPLIER/JITTER ATTENUATOR - Trays 制造商:Silicon Laboratories Inc 功能描述:IC TIMING CLOCK 36QFN 制造商:Silicon Laboratories Inc 功能描述:Clock Generators & Support Products G.8262 SyncE Clock Multiplier |
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