参数资料
型号: SI5327D-C-GMR
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: 243 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC36
封装: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
文件页数: 48/60页
文件大小: 715K
代理商: SI5327D-C-GMR
Si5327
52
Preliminary Rev. 0.4
29
28
CKOUT1–
CKOUT1+
OMulti
Output Clock 1.
Differential output clock with a frequency range of 2 kHz to
808 MHz. Output signal format is selected by SFOUT1_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
34
35
CKOUT2–
CKOUT2+
OMulti
Output Clock 2.
Differential output clock with a frequency range of 2 kHz to
808 MHz. Output signal format is selected by SFOUT2_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
36
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the Si5327.
0 = I2C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I2C or SPI
operation.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Pin #
Pin Name
I/O
Signal Level
Description
Note:
Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
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