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参数资料
| 型号： | SI5350A-A-GU |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 4/22页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 24QSOP |
| 标准包装： | 56 |
| 系列： | MultiSynth™ |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.25 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 管件 |
Si5350A
12
Rev. 0.9
Up to two frequency select pins are available on the Si5350A. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible.
The Si5350A uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350A. Similar to the FS pins, each OEB pin can
be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,
and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and
CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin
forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Figure 9. Example Configuration of a Pin-Controlled Output Enable
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS_0
FS_1
FS_0
0
1
F1_0, F1_3, F1_5
F2_0, F2_3, F2_5
Output Frequency
FS_1
0
1
F1_1, F1_2, F1_4
Output Frequency
CLKx
Frequency_A
Frequency_B
Full cycle completes before
changing to a new frequency
Frequency_A
New frequency starts
at its leading edge
Glitchless Frequency Changes
Cannot be controlled
by FS pins
Customizable FS Control
F2_1, F2_2, F2_4
MultiSynth 0
FS
MultiSynth 1
FS
MultiSynth 2
FS
MultiSynth 3
FS
MultiSynth 4
FS
MultiSynth 5
FS
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
OEB_0
OEB_1
OEB_0
0
1
CLK Enabled
CLK Disabled
Output State
OEB_2
OEB_1
0
1
CLK Enabled
CLK Disabled
Output State
OEB_2
0
1
CLK Enabled
CLK Disabled
Output State
Clock continues until
cycle is complete
CLKx
OEBx
Clock starts on the
first leading edge
Glitchless Output Enable
Customizable OEB Control
OEB
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5350A-A-GUR | 功能描述:时钟发生器及支持产品 Any-Rate Dual PLL 133MHz Clk 8 outputs RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GM | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GT | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 3 outputs, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GU | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Bxxxxx-GM | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 160 MHz Clock, 8 outputs with 50? output impedance, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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