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| 型号： | SI5350A-A-GU |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 5/22页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 24QSOP |
| 标准包装： | 56 |
| 系列： | MultiSynth™ |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.25 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 管件 |
Si5350A
Rev. 0.9
13
4.4. Design Considerations
The Si5350A is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.4.1. Power Supply Decoupling/Filtering
The Si5350A has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 F decoupling capacitor per power supply pin. This capacitor should
be mounted as close to the VDD and VDDO pins as possible without using vias.
4.4.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. It is important that power is applied to all supply pins (VDD, VDDOx) at the same
time. Unused VDDOx pins should be tied to VDD.
4.4.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
4.4.4. External Crystal Load Capacitors
The Si5350A provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
4.4.5. Unused Pins
Unused control pins (P0–P4) should be tied to GND.
Unused output pins (CLK0–CLK7) should be left floating.
4.4.6. Trace Characteristics
The Si5350A features various output current drives ranging from 2 to 8 mA (default). It is recommended to
configure the trace characteristics as shown in Figure 10 when an output drive setting of 8 mA is used.
Figure 10. Recommended Trace Characteristics with 8 mA Drive Strength Setting
Note: Jitter is only specified at 6 and 8 mA drive strength.
ZO = 85 ohms
Length = No Restrictions
CLK
(Optional resistor for
EMI management)
R = 0 ohms
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5350A-A-GUR | 功能描述:时钟发生器及支持产品 Any-Rate Dual PLL 133MHz Clk 8 outputs RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GM | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GT | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 3 outputs, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Axxxxx-GU | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock, 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5350A-Bxxxxx-GM | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 160 MHz Clock, 8 outputs with 50? output impedance, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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