参数资料
型号: SI5351B-A-GT
厂商: Silicon Laboratories Inc
文件页数: 7/72页
文件大小: 0K
描述: IC CLK GEN PLL BLANK CUST 10MSOP
标准包装: 50
系列: MultiSynth™
类型: *
PLL:
输入: 晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:8
差分 - 输入:输出: 无/无
频率 - 最大: 133MHz
除法器/乘法器: 是/无
电源电压: 2.25 V ~ 3.63 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
Si5351A/B/C
Preliminary Rev. 0.95
15
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and
timing diagram for the I2C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Write Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Read Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
Read Operation - Burst (Auto Address Increment)
Reg Addr +1
S
1 A
Slv Addr [6:0]
Data [7:0]
P
N
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
S
1 A
Slv Addr [6:0]
Data [7:0]
A
P
N
Data [7:0]
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