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| 型号： | SI5351C-A-GU |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 6/72页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 24QSOP |
| 标准包装： | 56 |
| 系列： | MultiSynth™ |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟，晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 133MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.25 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 管件 |
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Si5351A/B/C
14
Preliminary Rev. 0.95
4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
I2C interface. The following is a list of the common features that are controllable through the I2C interface. A
summary of register functions is shown in Section 7.
Read Status Indicators
Loss of signal (LOS) for the CLKIN input
Loss of lock (LOL) for PLLA and PLLB
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2n, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
I2C specification.
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I2C bus.
Figure 8. Si5351 I2C Slave Address
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
SCL
VDD
SDA
I2C Bus
INTR
A0
I2C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Si5351
>1k
4.7 k
Slave Address
1
0
0/1
A0
0
1
2
3
4
5
6
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5351C-A-GUR | 功能描述:时钟发生器及支持产品 Dual PLL 133MHz Clk Dual In and I2C 8Out RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5351C-Axxxxx-GM | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock with Dual Input and I2C, 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5351C-Axxxxx-GU | 功能描述:时钟发生器及支持产品 Any-Rate, Dual PLL 133MHz Clock with Dual Input and I2C, 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5351C-B02277-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK GENERATOR WITH FREQUENCY PLAN - Rail/Tube |
| SI5351C-B02277-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK GENERATOR WITH FREQUENCY PLAN - Tape and Reel |
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