参数资料
型号: SI8452BB-A-IS1
厂商: Silicon Laboratories Inc
文件页数: 20/36页
文件大小: 0K
描述: IC ISOLATOR DGTL 5CH 16SOIC
视频文件: Digital Isolation Overview
Digital Isolators vs. Optocouplers
标准包装: 48
系列: ISOpro
输入 - 1 侧/2 侧: 3/2
通道数: 5
电源电压: 2.7 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 150Mbps
传输延迟: 6ns
输出类型: 三态
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
工作温度: -40°C ~ 125°C
Si8450/51/52/55
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
Table 12. Si845x Logic Operation Table
Input
V I
H
L
X 7
X 7
1,2
EN
Input 1,2,3,4
H or NC
H or NC
L
H or NC
VDDI
State 1,5,6
P
P
P
UP
VDDO
State 1,5,6
P
P
P
P
V O Output 1,2
H
L
Hi-Z or L 8
L
Comments
Enabled, normal operation.
Disabled.
Upon transition of VDDI from unpowered to pow-
ered, V O returns to the same state as V I in less
than 1 μs.
X 7
L
UP
P
Hi-Z or L 8
Disabled.
X
7
X
7
P
UP
Undetermined Upon transition of VDDO from unpowered to pow-
ered, V O returns to the same state as V I within
1 μs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V O
returns to Hi-Z within 1 μs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. V I and V O are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to
VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 26 for more details.
20
Rev. 1.5
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