参数资料
型号: SI8452BB-A-IS1
厂商: Silicon Laboratories Inc
文件页数: 21/36页
文件大小: 0K
描述: IC ISOLATOR DGTL 5CH 16SOIC
视频文件: Digital Isolation Overview
Digital Isolators vs. Optocouplers
标准包装: 48
系列: ISOpro
输入 - 1 侧/2 侧: 3/2
通道数: 5
电源电压: 2.7 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 150Mbps
传输延迟: 6ns
输出类型: 三态
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
工作温度: -40°C ~ 125°C
Si8450/51/52/55
Table 13. Enable Input Truth Table 1
P/N
EN1 1,2 EN2 1,2
Operation
Si8450
Si8451
Si8452
Si8455
H
L
X
X
H
L
X
X
H
L
X
X
H
L
X
X
H
L
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state. 3
Output A5 enabled and follow input state.
Output A5 disabled and Logic Low or in high impedance state. 3
Outputs B1, B2, B3, B4 are enabled and follow input state.
Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state. 3
Outputs A4 and A5 are enabled and follow input state.
Outputs A4 and A5 are disabled and Logic Low or in high impedance state. 3
Outputs B1, B2, B3 are enabled and follow input state.
Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state. 3
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 3 μA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 26 for more details.
Rev. 1.5
21
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