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| 型号： | SI9122EDQ-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM VM 20-TSSOP |
| 标准包装： | 3,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 600kHz |
| 占空比： | 95% |
| 电源电压： | 10.5 V ~ 13.2 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
Si9122E
Vishay Siliconix
SPECIFICATIONS a
Test Conditions
Unless Otherwise Specified
f NOM = 500 kHz, V IN = 75 V
Limits
- 40 to 85 °C
Parameter
Symbol
V INDET = 7.5 V; 10.5 V ≤ V CC ≤ 13.2 V
Min. b
Typ. c
Max. b
Unit
Converter Supply Current (V CC )
Shutdown
I CC1
Shutdown, V INDET = 0 V
50
350
μ A
Converter Supply Current (V CC )
Switching Disabled
I CC2
V INDET < V REF
4
8
12
Switching w/o Load
Switching with C LOAD
I CC3
I CC4
V INDET > V REF, f NOM = 500 kHZ
V CC = 12 V, C DH = C DL = 3 nF
C SR H = C SR L = 0.3 nF
5
10
21
15
mA
Output MOSFET DH Driver (High-Side)
Output High Voltage
Output Low Voltage
V OH
V OL
Sourcing 10 mA
Sinking 10 mA
V BST - 0.3
V LX + 0.3
V
Boost Current
LX Current
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
I BST
I LX
I SOURCE
I SINK
t r
t f
V LX = 48 V, V BST = V LX + V CC
V LX = 48 V, V BST = V LX + V CC
V CC = 10.5 V
C DH = 3 nF
1.3
- 1.3
0.75
1.9
- 0.7
- 1.0
1.0
35
35
2.7
- 0.4
- 0.75
mA
A
ns
Output MOSFET DL Driver (Low-Side)
Output High Voltage
Output Low Voltage
V OH
V OL
Sourcing 10 mA
Sinking 10 mA
V CC - 0.3
0.3
V
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
I SOURCE
I SINK
t r
t f
V CC = 10.5 V
C DH = 3 nF
0.75
- 1.0
1.0
35
35
- 0.75
A
ns
Synchronous Rectifier (SR H , SR L ) Drivers
Output High Voltage
Output Low Voltage
V OH
V OL
Sourcing 10 mA
Sinking 10 mA
V CC - 0.4
0.4
V
t BBM1
T A = 25 °C, R BBM = 33 k Ω , V INDET = 4.8 V,
48
Break-Before-Make Time e
Peak Output Source
Peak Output Sink
Rise Time
Fall Time
t BBM2
t BBM3
t BBM4
I SOURCE
I SINK
t r
t f
V EP = 0 V, V IN = 48 V
T A = 25 °C, R BBM = 33 k Ω , BST= 60 V,
V INDET = 4.8 V, V EP = 0 V, V IN = 48 V = LX
V CC = 10.5 V
C DH = 3 nF
9
24
18
- 100
100
35
35
ns
mA
ns
Voltage Mode
Error Amplifier
t d1DH
t d2DL
Input to High-Side Switch Off
Input to Low-Side Switch Off
< 200
< 200
ns
Current Mode
Current Amplifier
t d3DH
t d4DL
Input to High-Side Switch Off
Input to Low-Side Switch Off
< 200
< 200
ns
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. F MIN when V C L_CONT at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature.
e. See Figure 3 for Break-Before-Make time definition.
f. V UVLO tracks V REG1 by a diode drop.
g. Guaranteed by design and characterization, not tested in production.
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
5
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