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参数资料
| 型号： | SIP11206DLP-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 8/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM MLP44-16 |
| 标准包装： | 2,500 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 50% |
| 电源电压： | 10.5 V ~ 13.2 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | PowerPAK? MLP44-16 |
| 包装： | 带卷 (TR) |
SiP11206
Vishay Siliconix
CIRCUIT FOR FREQUENCY SYNCHRONIZATION
220 pF
100
2 N 3904
SY N C I N
1k
DETAILED OPERATIONAL DESCRIPTION
C osc
SiP11206
Start Up
The controller supply (V CC ) is linearly regulated up to its
target voltage V REG by the on chip pre-regulator circuit.
During power up with V INDET ramping up from 0, the V CC
capacitor minimum charge current is 20 mA and the
pre-regulator voltage is typically 9.3 V. As V INDET exceeds
V REF , the DL/DH outputs are capable of driving 3 nF
MOSFET gate capacitances and hence the pre-regulator
load regulation can easily handle 120 μA to 20 mA load step
with a typical load regulation of 1 %. Current into the external
V CC capacitor is limited to typically 20 mA by the internal
pre-regulator unless an external power source is connected
to V CC pin. This source may be a DC supply or from V IN by
connecting a PNP pass transistor between V IN and V CC . The
V CC pin is protected by a 20 mA clamp when this pin exceeds
14.5 V. The clamp turns on when V CC is between 14.5 V and
16 V. When V CC exceeds the UVLO voltage (UVLO H ) a soft
start cycle of the switch mode supply is initiated. The V CC
supply continues to be charged by the pre-regulator until V CC
equals V REG . During this period, between UVLO H and V REG ,
excessive load may result in V CC falling below UVLO H and
stopping switch mode operation. This situation is avoided by
the hysteresis between V REG and UVLO Off-Threshold level
UVLO L .
PWM Operation
During startup, DL always turns on before DH and both
switch on and off at half the oscillator frequency. The driver
duty cycle increases as SS voltage increases, since the SS
comparator sets the ON pulse width by comparing the SS
ramp voltage with the oscillator ramp voltage. When SS
ramp reaches a voltage that equals to R DB voltage, the PWM
comparator, which compares R DB voltage to the oscillator
ramp, takes over and the maximum duty cycle is now set by
the oscillator ramp and R DB voltage. Mathematically, the
total duty cycle is determined by the following formula:
D TOTAL = R DB /R OSC
And the duty cycle on DL or DH will be approximately half of
D TOTAL . Please note that due to oscillator comparator
overshoot the exact duty cycle calculated using above
www.vishay.com
8
formula may be slightly different. The PWM operation during
start up can be better understood by referring to "Timing
diagram and soft start duty cycle control" graph. The soft
start completion voltage at SS pin is clamped above the
internal ramp waveform's upper turning point.
Soft Start
The soft start circuit plays an important role in protecting the
controller. At startup it prevents high in-rush current. During
a normal start-up sequence (V CS < V MOC . V CS is the voltage
at CS pin), or following any event that would cause a hiccup-
and-soft-start sequence, C SS will be charged from about 0 V
to a final voltage of 4.8 V at a 20 μA rate. As the voltage on
the C SS rises towards the final voltage, the maximum
permitted DL and DH duty cycles will increase from 0 % to a
maximum defined by the R DB resistor.
When a mild fault condition is detected (V CS = V MOC ), C SS
goes into a hiccup mode until fault condition is removed. The
hiccup is activated when C SS discharges to 0.85 V SS at
20 μA and subsequently at 0.4 μA until the fault condition is
removed. Refer to "Fault Conditions and Responses" for
details.
Fault Conditions and Responses
The faults that can cause a hiccup-and-retry cycle are
moderate over-current (MOC), severe over-current (SOC),
chip level UVLO, system level UVLO, and over temperature
protection (OTP).
Prior to detailing the various fault conditions and responses,
some definitions are given:
1. A complete switching period, T, consists of two oscillator
cycles, T DL and T DH .
2. T DL (T DH ) is the oscillator cycle during which the DL (DH)
output is in the high state.
3. T is defined as starting at the beginning of T DL , and
terminating at the end of T DH .
Response to MOC Faults (V MOC < V CS < V SOC ):
Once SiP11206 has completed a normal soft-start cycle, V SS
will be clamped at 4.5 V, allowing the maximum possible duty
cycle on DL and DH.
Document Number: 69232
S-81795-Rev. C, 04-Aug-08
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