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参数资料
| 型号： | SK100E111PJ |
| 元件分类： | 时钟及定时 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 1/6页 |
| 文件大小： | 159K |
| 代理商： | SK100E111PJ |
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 3 / September 4, 2002
The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single-
ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-
device, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same VCCO) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
The SK10/100E111 provides VBB output for either
single-ended use or as a DC bias for AC coupling to
the device. The VBB output pin should be used only
as a DC bias for the E111 as its current sink/source
capability is limited.
Whenever used, the VBB pin
should be bypassed to VCC via a 0.01 F capacitor.
SK10/100E111
1:9 Differential
Clock Driver
Description
Features
Functional Block Diagram
Low Skew
Guaranteed Skew Spec
Differential Design
VBB Output
Enable Input
Extended 100E VEE Range of –4.2 to –5.5V
Internal 75K
Input Pulldown Resistors
Compatible with MC10/100E111
Specified Over Industrial Temperature Range:
–40oC to +85oC
ESD Protection of >4000V
Available in 28-Lead PLCC Package
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
Q4*
Q5
Q5*
Q6
Q6*
Q7
Q7*
Q8
Q8*
IN
IN*
EN*
VBB
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PDF描述 |
|---|---|
| SK10EL57WU | 10E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, UUC |
| SK1503T | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| SK2200LF | LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| SLB-24MG | SINGLE COLOR LED, GREEN, 4 mm |
| SLB-2 | PASSIVE DELAY LINE, TRUE OUTPUT, PSIP7 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SK100E111PJT | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:1:9 Differential Clock Driver |
| SK100E116 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E116PJ | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E116PJT | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E131 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:4-Bit D Flip-Flop |
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