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参数资料
| 型号： | SK100E111PJ |
| 元件分类： | 时钟及定时 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 5/6页 |
| 文件大小： | 159K |
| 代理商： | SK100E111PJ |
5
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TEST AND MEASUREMENT PRODUCTS
SK10/100E111
Revision 3 / September 4, 2002
IN
IN*
EN*
Q*
Q
th
50%
≤75 mV
Figure 1. Setup Time
Figure 2. Hold Time
Figure 3. Release Time
IN
IN*
EN*
Q*
Q
ts
50%
≤75 mV
IN
IN*
EN*
Q*
Q
tr
50%
Notes:
1.
10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2.
100E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3.
Differential input voltage required to obtain a full ECL swing on the outputs.
4.
VCMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of V
CMR
range varies 1:1 with VEE and is equal to VEE+2.6V.
5.
The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.
6.
The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.
7.
Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the
50% point of a positive transition on Q (or a negative transition on Q*). Disable is defined as the
propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative
transition on Q (or a positive transition on Q*).
8.
The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.
9.
The setup time is the minimum time that EN* must be asserted prior to the next transition of IN/IN to
prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 1).
10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive
going IN* to prevent an output response greater than ±75 mV to the IN/IN transition (see Figure 2).
11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to
ensure an output response that meets the specified IN to Q propagation delay and output transition times
(see Figure 3).
12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the
propagation delay.
The VPP(min) is AC limited for the E111 as a differential input as low as 250 mV
will still produce full ECL levels at the output.
13. Voltages referenced to VCC = 0V.
14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
AC Characteristics (continued)
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相关代理商/技术参数 |
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|---|---|
| SK100E111PJT | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:1:9 Differential Clock Driver |
| SK100E116 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E116PJ | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E116PJT | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Quint Differential Line Receiver |
| SK100E131 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:4-Bit D Flip-Flop |
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