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参数资料
| 型号： | SL15100ZI-XXXT |
| 元件分类： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.173 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件页数： | 12/16页 |
| 文件大小： | 380K |
| 代理商： | SL15100ZI-XXXT |
Rev 2.0, August 10, 2008
Page 5 of 16
SL15100
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
FIN1
Crystal or Ceramic Resonator
8
-
48
MHz
Input Frequency Range
FIN2
External Clock
8
-
166
MHz
Output Frequency Range
FOUT1
SSCLK
3
-
200
MHz
Output Frequency Range
FOUT2
REFCLK, crystal or resonator input
0.25
-
48
MHz
Output Frequency Range
FOUT3
REFCLK, clock input
0.25
-
166
MHz
Output Duty Cycle
DC1
SSCLK
45
50
55
%
Output Duty Cycle
DC2
REFCLK
45
50
55
%
Input Duty Cycle
DCIN
Clock Input, Pin 3
40
50
60
%
Output Rise/Fall Time
tr/f1
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
4.00
4.80
ns
Output Rise/Fall Time
tr/f2
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
2.00
2.40
ns
Output Rise/Fall Time
tr/f3
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
1.40
1.70
ns
Output Rise/Fall Time
tr/f4
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
1.10
1.35
ns
Output Rise/Fall Time
tr/f5
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
0.85
1.00
ns
Output Rise/Fall Time
tr/f6
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
0.70
0.85
ns
Output Rise/Fall Time
tr/f7
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
-
0.55
0.67
ns
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ1
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=Off
-
90
120
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ2
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=Off
-
100
130
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ3
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=Off
-
120
160
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ4
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
100
130
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ5
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
-
105
140
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ6
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
-
180
240
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ7
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
80
100
ps
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