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参数资料
| 型号： | SL15100ZI-XXXT |
| 元件分类： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.173 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件页数： | 4/16页 |
| 文件大小： | 380K |
| 代理商： | SL15100ZI-XXXT |
Rev 2.0, August 10, 2008
Page 12 of 16
SL15100
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ2
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=Off
-
125
160
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ3
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=Off
-
125
160
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ4
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
145
185
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ5
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
-
125
160
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ6
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
-
215
280
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ7
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
-
105
130
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ8
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
-
125
160
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CCJ9
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
-
165
220
ps
Power-down Time
tPD
Time from PD# falling edge to Hi-Z at
outputs (Asynchronous)
-
180
350
ns
Power-up Time
(Crystal or Clock)
tPU
Time from PD# rising edge to valid
frequency at outputs (Asynchronous)
-
3.5
5.0
ms
Power Supply Ramp
Time
tPSR
Time for VDD reaching minimum
specified value and monolithic power
supply ramp
-
12
ms
Output Enable Time
tOE
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
180
350
ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
180
350
ns
Spread Percent Range
SPR
SSCLK-1/2
0.25
-
5.0
%
Spread Percent Variation
ΔSS%
Variation of programmed Spread %
-20
-
20
%
Modulation Frequency
FMOD
Programmable, 31.5 kHz standard
25
31.5
120
kHz
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