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参数资料
| 型号： | SL15316ZI-XXX |
| 元件分类： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, ROHS COMPLIANT, TSSOP-16 |
| 文件页数： | 9/12页 |
| 文件大小： | 276K |
| 代理商： | SL15316ZI-XXX |
Rev 1.0, August 7, 2008
Page 6 of 12
SL15316
Operating Supply Current
IDD
FIN=25MHz Clock, all 5 clocks
are at 66MHz, +/-1.0% Spread.
CL=0, VDD=VDDO=3.3V
-
9.0
TBD
mA
Standby Current
ISBC
If programmed PD#=GND
-
70
100
μA
Output Leakage Current
IOL
For Pins programmed as
SSCLK or REFOUT and if PD#
or OE is programmed.
PD#=0 or OE=1
-10
-
10
μA
Minimum programming value
-
7
-
pF
Programmable Input
Capacitance at Pins 3 and 4
PCin
PCout
Maximum programming value
-
38
-
pF
Input Capacitance
CIN2
Pins programmed as PD#, OE,
SSON or FS
-
4
6
pF
Load Capacitance
CL
For all pins programmed as
SSCLK or REFCLK
-
15
pF
AC Electrical Characteristics (C and I-Grades)
Unless otherwise stated VDD= 3.3V+/- 10% and CL=15pF
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
FIN1
Crystal or Ceramic Resonator
8
-
48
MHz
Input Frequency Range
FIN2
External Clock
3
-
166
MHz
Output Frequency Range FOUT1
SSCLK
3
-
200
MHz
Output Frequency Range FOUT2
REFCLK, crystal or resonator input
0.25
-
48
MHz
Output Frequency Range FOUT3
REFCLK, clock input
0.25
-
166
MHz
Output Duty Cycle
DC1
SSCLK
45
50
55
%
Output Duty Cycle
DC2
REFCLK
45
50
55
%
Input Duty Cycle
DCIN
Clock Input, Pin 3
40
50
60
%
Output Rise/Fall Time
tr/f1
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
3.8
-
ns
Output Rise/Fall Time
tr/f2
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
1.9
-
ns
Output Rise/Fall Time
tr/f3
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
1.4
-
ns
Output Rise/Fall Time
tr/f4
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
1.0
-
ns
Output Rise/Fall Time
tr/f5
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
0.85
-
ns
Output Rise/Fall Time
tr/f6
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
0.65
-
ns
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