参数资料
型号: SL28541BZI-2
厂商: Silicon Laboratories Inc
文件页数: 21/28页
文件大小: 0K
描述: IC CLOCK CK505 MOBILE 56TSSOP
标准包装: 35
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 时钟,晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:21
差分 - 输入:输出: 无/是
频率 - 最大: 400MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
SL28541-2
...................... DOC #: SP-AP-0064 (Rev. AB) Page 28 of 28
Document History Page
Document Title: SL28541-2 Clock Generator for IntelMobile Chipset
DOC #: SP-AP-0064 (Rev. AB)
REV.
ECR#
Issue
Date
Orig. of
Change
Description of Change
1.0
1/01/07
JMA
New data sheet
1.1
6/15/07
BEN
Change ordering number to SL28541BQC
1.2
9/18/07
BEN
VDDIO range change from 1.25V to 1.05V
1.3
10/31/07
BEN
1. Added 64 TSSOP pin definitions
2. Added 64 TSSOP package dimension
3. Byte1[2] is changed from 0 to 1 and Byte1[1] is changed from 1 to 0 by power up
default
4. Changed Byte 13 bit 5 spread percentage from -1% to -0.45%
5. Updated revision ID
1.4
12/15/07
SLI
1. Updated Pin Definition table
2. Updated Table 7. PLL3/SE Configuration Table
1.5
1/23/08
JMA
1. Changed Byte 13 Bit 5 to replace 0.45% spread to 1% spread.
2. Changed 27MHz period spec to be reflect down spread.
3. Changed 27MHz CCJ spec from 200ps to 250ps.
1.6
7/8/08
JMA
1. Changed maximum operating temperature range from 85C to 70C
2. Added note on Pb-free, Halogen-free, and RoHS compliant
3. Added note on extended temperature
4. Added Mitsui package
1.7
2/23/09
JMA
1. Added 64-TSSOP package on page 1.
2. Change operating temperature back to 85C
1.8
3/31/09
JMA
1. Updated QFN packge information
2. Udpated Slew rate measurement for 27MHz clocks
3. Updated Tperiod for CPU clock at 100MHz
4. Corrected Byte 7 Revision ID
5. Corrected Byte 8 Device ID
6. Added PWRDWN IDD Spec
1.9
4/27/09
JMA
1. Corrected Reserved bit in Byte18
2. Corrected Reserved bit in Byte 20
3. Corrected wording for PD to PWRDWN
4. Added “F” in pF in Figure 2
5. Removed Cypress package marking
2.0
9/10/09
JMA
1. Updated QFN package information
AA
1454
04/09’/10
JMA
1. Added CLKIN feature.
2. Updated Absolut spec
3. Move location of Output Drive Satus & PLL3/SE Configue tables
4. Combined commercial and industrial temperature grade
5. Updated VDD_IO voltage
AB
1641
06/08/10
JMA
1. Updated VDDIO max spec
2. Updated block diagram.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, represen-
tation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or
incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sus-
tain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
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