参数资料
型号: SL28541BZI-2
厂商: Silicon Laboratories Inc
文件页数: 23/28页
文件大小: 0K
描述: IC CLOCK CK505 MOBILE 56TSSOP
标准包装: 35
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 时钟,晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:21
差分 - 输入:输出: 无/是
频率 - 最大: 400MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
SL28541-2
........................ DOC #: SP-AP-0064 (Rev. AB) Page 4 of 28
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
56
SMB_CLK
I
SMBus compatible SCLOCK.
56 TSSOP Pin Definition (continued)
Pin No.
Name
Type
Description
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
0
266 MHz
100 MHz
33 MHz
27 MHz
14.318 MHz
96 MHz
48 MHz
0
1
133 MHz
0
1
0
200 MHz
0
1
166 MHz
1
0
333 MHz
1
0
1
100 MHz
1
0
400 MHz
1
Reserved
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code–8 bits
18:11
Command Code–8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count–8 bits
20
Repeat start
28
Acknowledge from slave
27:21
Slave address–7 bits
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